From: Thomas Gleixner <tglx@linutronix.de>
To: "Zhang, Rui" <rui.zhang@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "Gross, Jurgen" <jgross@suse.com>,
"mikelley@microsoft.com" <mikelley@microsoft.com>,
"arjan@linux.intel.com" <arjan@linux.intel.com>,
"x86@kernel.org" <x86@kernel.org>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"ray.huang@amd.com" <ray.huang@amd.com>,
"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>,
"Sivanich, Dimitri" <dimitri.sivanich@hpe.com>,
"wei.liu@kernel.org" <wei.liu@kernel.org>
Subject: Re: [patch V3 27/40] x86/cpu: Provide a sane leaf 0xb/0x1f parser
Date: Sat, 12 Aug 2023 22:04:48 +0200 [thread overview]
Message-ID: <87350ogh7j.ffs@tglx> (raw)
In-Reply-To: <8e5bbbc91ff9f74244efe916a4113999abc52213.camel@intel.com>
On Sat, Aug 12 2023 at 08:21, Rui Zhang wrote:
> On Wed, 2023-08-02 at 12:21 +0200, Thomas Gleixner wrote:
>> +
>> +/*
>> + * Use a lookup table for the case that there are future types > 6
>> which
>> + * describe an intermediate domain level which does not exist today.
>> + *
>> + * A table will also be handy to parse the new AMD 0x80000026 leaf
>> which
>> + * has defined different domain types, but otherwise uses the same
>> layout
>> + * with some of the reserved bits used for new information.
>> + */
>> +static const unsigned int topo_domain_map[MAX_TYPE] = {
>> + [SMT_TYPE] = TOPO_SMT_DOMAIN,
>> + [CORE_TYPE] = TOPO_CORE_DOMAIN,
>> + [MODULE_TYPE] = TOPO_MODULE_DOMAIN,
>> + [TILE_TYPE] = TOPO_TILE_DOMAIN,
>> + [DIE_TYPE] = TOPO_DIE_DOMAIN,
>> + [DIEGRP_TYPE] = TOPO_PKG_DOMAIN,
>
> May I know why DIEGRP_TYPE is mapped to TOPO_PKG_DOMAIN?
Where else should it go? It's the topmost, no? But diegrp is a
terminoligy which is not used in the kernel
>> +
>> + if (sl.type >= maxtype) {
>
> It is still legal to have sparse type value in the future, and then
> this check will break.
> IMO, it is better to use a function to convert type to domain, and
> check for unknown domain here, say, something like
Why? If somewhere in the future Intel decides to add UBER_TILE_TYPE,
then this will be a type larger than DIEGRP_TYPE. maxtype will then
cover the whole thing and the table will map it to the right place.
Even if in their infinite wisdom the HW folks decide to make a gap, then
the table can handle it simply by putting an invalid value into the gap
and checking for that.
Serioulsy we don't need a switch case for that.
>> + /*
>> + * As the subleafs are ordered in domain level order,
>> this
>> + * could be recovered in theory by propagating the
>> + * information at the last parsed level.
>> + *
>> + * But if the infinite wisdom of hardware folks
>> decides to
>> + * create a new domain type between CORE and MODULE
>> or DIE
>> + * and DIEGRP, then that would overwrite the CORE or
>> DIE
>> + * information.
>
> Sorry that I'm confused here.
>
> Say, we have CORE, FOO, MODULE, then the subleave of FOO must be higher
> than CORE but lower than MODULE.
> so we parse CORE first and propagates the info to FOO/MODULE, and then
> parse FOO and propagate to MODULE, and parse MODULE in the end.
> How could we overwrite the info of a lower level?
We don't know about this new thing yet. So where should we propagate to?
We could say, last was core so we stick the new thing into module, but
do we know that's correct? Do we know there is a module actually. Let me
rephrase that comment.
>> + *
>> + * Refuse to implement monstrosity, emit an error and try
>> + * to survive.
>> + */
>> + pr_err_once("Topology: leaf 0x%x:%d Unknown domain type %u\n",
>> + leaf, subleaf, sl.type);
>> + return true;
>
> Don't want to be TLDR, I can think of a couple cases that breaks Linux
> in different ways if we ignore the cpu topology info of an unknown
> level.
Come on. If Intel manages it to create a new level then it's not rocket
science to integrate support for that a long time before actual silicon
ships. So what will break? The machines of people who use ancient
kernels on modern hardware? They can keep the pieces.
> So I just want to understand the strategy here, does this mean that
> we're not looking for a future proof solution, and instead we are
> planning to take future updates (patch enum topo_types/enum
> x86_topology_domains/topo_domain_map) whenever a new level is
> invented?
You need that anyway, no?
> With this, we can guarantee that all the available topology information
> are always valid, even when running on future platforms.
I know that it can be made work, but is it worth the extra effort? I
don't think so.
Thanks,
tglx
next prev parent reply other threads:[~2023-08-12 20:06 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-02 10:20 [patch V3 00/40] x86/cpu: Rework the topology evaluation Thomas Gleixner
2023-08-02 10:20 ` [patch V3 01/40] cpu/SMT: Make SMT control more robust against enumeration failures Thomas Gleixner
2023-08-04 17:50 ` Borislav Petkov
2023-08-04 20:01 ` Thomas Gleixner
2023-08-02 10:21 ` [patch V3 02/40] x86/apic: Fake primary thread mask for XEN/PV Thomas Gleixner
2023-08-04 18:12 ` Borislav Petkov
2023-08-04 20:02 ` Thomas Gleixner
2023-08-02 10:21 ` [patch V3 03/40] x86/cpu: Encapsulate topology information in cpuinfo_x86 Thomas Gleixner
2023-08-02 10:21 ` [patch V3 04/40] x86/cpu: Move phys_proc_id into topology info Thomas Gleixner
2023-08-02 10:21 ` [patch V3 05/40] x86/cpu: Move cpu_die_id " Thomas Gleixner
2023-08-09 14:32 ` Zhang, Rui
2023-08-09 15:14 ` Thomas Gleixner
2023-08-02 10:21 ` [patch V3 06/40] scsi: lpfc: Use topology_core_id() Thomas Gleixner
2023-08-02 10:21 ` [patch V3 07/40] hwmon: (fam15h_power) " Thomas Gleixner
2023-08-02 10:21 ` [patch V3 08/40] x86/cpu: Move cpu_core_id into topology info Thomas Gleixner
2023-08-02 10:21 ` [patch V3 09/40] x86/cpu: Move cu_id " Thomas Gleixner
2023-08-02 10:21 ` [patch V3 10/40] x86/cpu: Remove pointless evaluation of x86_coreid_bits Thomas Gleixner
2023-08-02 10:21 ` [patch V3 11/40] x86/cpu: Move logical package and die IDs into topology info Thomas Gleixner
2023-08-02 10:21 ` [patch V3 12/40] x86/cpu: Move cpu_l[l2]c_id " Thomas Gleixner
2023-08-02 10:21 ` [patch V3 13/40] x86/apic: Use BAD_APICID consistently Thomas Gleixner
2023-08-02 10:21 ` [patch V3 14/40] x86/apic: Use u32 for APIC IDs in global data Thomas Gleixner
2023-08-02 10:21 ` [patch V3 15/40] x86/apic: Use u32 for check_apicid_used() Thomas Gleixner
2023-08-02 10:21 ` [patch V3 16/40] x86/apic: Use u32 for cpu_present_to_apicid() Thomas Gleixner
2023-08-02 10:21 ` [patch V3 17/40] x86/apic: Use u32 for phys_pkg_id() Thomas Gleixner
2023-08-02 10:21 ` [patch V3 18/40] x86/apic: Use u32 for [gs]et_apic_id() Thomas Gleixner
2023-08-02 10:21 ` [patch V3 19/40] x86/apic: Use u32 for wakeup_secondary_cpu[_64]() Thomas Gleixner
2023-08-10 7:58 ` Qiuxu Zhuo
2023-08-02 10:21 ` [patch V3 20/40] x86/cpu/topology: Cure the abuse of cpuinfo for persisting logical ids Thomas Gleixner
2023-08-02 10:21 ` [patch V3 21/40] x86/cpu: Provide debug interface Thomas Gleixner
2023-08-02 10:21 ` [patch V3 22/40] x86/cpu: Provide cpuid_read() et al Thomas Gleixner
2023-08-02 10:21 ` [patch V3 23/40] x86/cpu: Provide cpu_init/parse_topology() Thomas Gleixner
2023-08-04 8:14 ` K Prateek Nayak
2023-08-04 8:28 ` Thomas Gleixner
2023-08-04 8:34 ` K Prateek Nayak
2023-08-12 6:41 ` Zhang, Rui
2023-08-12 8:00 ` Zhang, Rui
2023-08-14 6:26 ` Thomas Gleixner
2023-08-14 7:11 ` Zhang, Rui
2023-08-13 13:30 ` Zhang, Rui
2023-08-13 14:36 ` Thomas Gleixner
2023-08-14 6:20 ` Thomas Gleixner
2023-08-14 6:42 ` Zhang, Rui
2023-08-02 10:21 ` [patch V3 24/40] x86/cpu: Add legacy topology parser Thomas Gleixner
2023-08-02 10:21 ` [patch V3 25/40] x86/cpu: Use common topology code for Centaur and Zhaoxin Thomas Gleixner
2023-08-02 10:21 ` [patch V3 26/40] x86/cpu: Move __max_die_per_package to common.c Thomas Gleixner
2023-08-02 10:21 ` [patch V3 27/40] x86/cpu: Provide a sane leaf 0xb/0x1f parser Thomas Gleixner
2023-08-12 8:21 ` Zhang, Rui
2023-08-12 20:04 ` Thomas Gleixner [this message]
2023-08-13 15:04 ` Thomas Gleixner
2023-08-14 8:25 ` Zhang, Rui
2023-08-14 12:26 ` Thomas Gleixner
2023-08-14 14:48 ` Brown, Len
2023-08-14 16:13 ` Thomas Gleixner
2023-08-15 19:30 ` Brown, Len
2023-08-17 9:09 ` Thomas Gleixner
2023-08-18 5:01 ` Brown, Len
2023-08-21 10:27 ` Thomas Gleixner
2023-08-30 2:46 ` Brown, Len
2023-08-30 12:39 ` Thomas Gleixner
2023-09-01 3:09 ` Brown, Len
2023-09-01 7:45 ` Thomas Gleixner
2023-08-14 15:28 ` Zhang, Rui
2023-08-14 17:12 ` Thomas Gleixner
2023-08-02 10:21 ` [patch V3 28/40] x86/cpu: Use common topology code for Intel Thomas Gleixner
2023-08-02 10:21 ` [patch V3 29/40] x86/cpu/amd: Provide a separate accessor for Node ID Thomas Gleixner
2023-08-02 10:21 ` [patch V3 30/40] x86/cpu: Provide an AMD/HYGON specific topology parser Thomas Gleixner
2023-08-02 19:28 ` Michael Kelley (LINUX)
2023-08-02 19:46 ` Thomas Gleixner
2023-08-02 19:51 ` [patch V3a " Thomas Gleixner
2023-08-11 12:58 ` Pu Wen
2023-08-11 17:11 ` Thomas Gleixner
2023-08-12 3:58 ` Pu Wen
2023-10-13 9:38 ` [tip: x86/core] x86/cpu/hygon: Fix the CPU topology evaluation for real tip-bot2 for Pu Wen
2023-08-02 10:21 ` [patch V3 31/40] x86/smpboot: Teach it about topo.amd_node_id Thomas Gleixner
2023-08-02 10:21 ` [patch V3 32/40] x86/cpu: Use common topology code for AMD Thomas Gleixner
2023-08-02 10:21 ` [patch V3 33/40] x86/cpu: Use common topology code for HYGON Thomas Gleixner
2023-08-11 13:00 ` Pu Wen
2023-08-11 17:11 ` Thomas Gleixner
2023-08-02 10:21 ` [patch V3 34/40] x86/mm/numa: Use core domain size on AMD Thomas Gleixner
2023-08-02 10:21 ` [patch V3 35/40] x86/cpu: Make topology_amd_node_id() use the actual node info Thomas Gleixner
2023-08-02 10:21 ` [patch V3 36/40] x86/cpu: Remove topology.c Thomas Gleixner
2023-08-02 10:21 ` [patch V3 37/40] x86/cpu: Remove x86_coreid_bits Thomas Gleixner
2023-08-02 10:21 ` [patch V3 38/40] x86/apic: Remove unused phys_pkg_id() callback Thomas Gleixner
2023-08-02 10:21 ` [patch V3 39/40] x86/xen/smp_pv: Remove cpudata fiddling Thomas Gleixner
2023-08-02 10:22 ` [patch V3 40/40] x86/apic/uv: Remove the private leaf 0xb parser Thomas Gleixner
2023-08-02 11:56 ` [patch V3 00/40] x86/cpu: Rework the topology evaluation Juergen Gross
2023-08-03 0:07 ` Sohil Mehta
2023-08-03 3:44 ` Michael Kelley (LINUX)
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