From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48A6AEB64DC for ; Thu, 6 Jul 2023 14:27:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231902AbjGFO1v (ORCPT ); Thu, 6 Jul 2023 10:27:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbjGFO1t (ORCPT ); Thu, 6 Jul 2023 10:27:49 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49A6710F5 for ; Thu, 6 Jul 2023 07:27:48 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DC4AF61983 for ; Thu, 6 Jul 2023 14:27:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 449FFC433C7; Thu, 6 Jul 2023 14:27:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1688653667; bh=XjMcz5uZNstuRDH3jnBWjbSJFiV7skHvPFlp98zFaNI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=BhAi0ogwapMqRb9bpapU3oUWnc7D4mZZ/5AokTrCdVsbl2BdVT8SJyQdWKJ+VC1Fk v3yy86953vnQPJI3nGDoREpbFSt8as5YUGBSRKx6AsGMRkOXbAlZXdjOyJrIkORYCy YeStLA8+YflkUTqkGJ2lhVq41/1NhacWHTx9CmjetWfE5r29mJEypyKVd5TALcIRqE sbdye9kHbOYkLY8kkdLUmu3n/B5k9EilXDMNcXRHCw7SjWfu+v4M3t41dvaD+kpt/e G0Rk0/05pAAoDhG2BAHT04XZKysR7Jp7Do3dbLTpbyzw52RVthudlnw7wFAoMlqFAX 5N9P0FJZD55xw== Received: from 84-53-99-172.bbserv.nl ([84.53.99.172] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qHPxQ-00AxTm-Ul; Thu, 06 Jul 2023 15:27:45 +0100 Date: Thu, 06 Jul 2023 15:27:36 +0100 Message-ID: <873521yv1j.wl-maz@kernel.org> From: Marc Zyngier To: Mostafa Saleh Cc: oliver.upton@linux.dev, Sudeep Holla , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, tabba@google.com, qperret@google.com, will@kernel.org, catalin.marinas@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, james.morse@arm.com, bgardon@google.com, gshan@redhat.com Subject: Re: [PATCH v3] KVM: arm64: Use BTI for nvhe In-Reply-To: References: <20230530150845.2856828-1-smostafa@google.com> <20230704134136.a5znw4jupt5yp5kg@bogus> <20230704143339.cqrvntq7rmmb2on3@bogus> <20230704192529.d4x2p7ndz2dc4q52@bogus> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 84.53.99.172 X-SA-Exim-Rcpt-To: smostafa@google.com, oliver.upton@linux.dev, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, tabba@google.com, qperret@google.com, will@kernel.org, catalin.marinas@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, james.morse@arm.com, bgardon@google.com, gshan@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mostafa, On Thu, 06 Jul 2023 13:49:04 +0100, Mostafa Saleh wrote: > > Hi Marc and Oliver, > > I was double checking that nothing else was missed. > > I found there is another problem for hw that has BTI and is affected > by specterv3a. > > "br'' instructions are generated at runtime for the vector > table(__bp_harden_hyp_vecs). These branches would land on vectors > in __kvm_hyp_vector at offset 8. > > As all the macros are defined with valid_vect/invalid_vect, it is > sufficient to add "bti j" there at the correct offset. > > I am not sure if such hardware exists. I tested this with a stubbed > "has_spectre_v3a" which confirms the issue and the fix. Thanks for the heads up. Fortunately, there is no such HW as far as I can tell. Only Cortex-A57 and A72 are affected by this (and the only two CPUs for which we engage the mitigation), and they are way too old to know about BTI. > Please let me know if this fix suitable, I can include it with the other fix in > "[PATCH] KVM: arm64: Add missing BTI instruction in kvm_host_psci_cpu_entry" > > diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S > index 8f3f93fa119e..175c030379e3 100644 > --- a/arch/arm64/kvm/hyp/hyp-entry.S > +++ b/arch/arm64/kvm/hyp/hyp-entry.S > @@ -154,6 +154,12 @@ SYM_CODE_END(\label) > esb > stp x0, x1, [sp, #-16]! > 662: > + /* > + * Specter vectors __bp_harden_hyp_vecs generate br instructions at runtime > + * that jump at offset 8 at __kvm_hyp_vector. > + * As hyp .text is guarded section, it needs bti j. > + */ > + bti j > b \target > > check_preamble_length 661b, 662b > @@ -165,6 +171,8 @@ check_preamble_length 661b, 662b > nop > stp x0, x1, [sp, #-16]! > 662: > + /* Check valid_vect */ > + bti j > b \target > > check_preamble_length 661b, 662b This looks correct to me. If you can respin you initial patch (with maybe a slightly more generic subject) so that Oliver can pick it up as part of the next batch of fixes, that'd be great. Thanks, M. -- Without deviation from the norm, progress is not possible.