From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F148C433F5 for ; Thu, 28 Oct 2021 08:34:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E11BB610CF for ; Thu, 28 Oct 2021 08:34:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229987AbhJ1IhY (ORCPT ); Thu, 28 Oct 2021 04:37:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:51806 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229626AbhJ1IhX (ORCPT ); Thu, 28 Oct 2021 04:37:23 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ECEC7610C8; Thu, 28 Oct 2021 08:34:56 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mg0sA-0025Rg-TI; Thu, 28 Oct 2021 09:34:55 +0100 Date: Thu, 28 Oct 2021 09:34:54 +0100 Message-ID: <8735olbl8x.wl-maz@kernel.org> From: Marc Zyngier To: Zhiyuan Dai Cc: Thomas Gleixner , Hector Martin , Will Deacon , linux-kernel@vger.kernel.org Subject: Re: [PATCH] irqchip/gic-v3: Fix EOImode semantics in git_cpu_sys_reg_init() In-Reply-To: <1635408092-5259-1-git-send-email-daizhiyuan@phytium.com.cn> References: <1635408092-5259-1-git-send-email-daizhiyuan@phytium.com.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: daizhiyuan@phytium.com.cn, tglx@linutronix.de, marcan@marcan.st, will@kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Zhiuyan, On Thu, 28 Oct 2021 09:01:31 +0100, Zhiyuan Dai wrote: > > ICC_CTLR_EL1 is a 64-bit register.EOImode, bit [1] EOI mode > for the current Security state. > > current code semantics is set ICC_CTLR_EL1 register to zero. > This patch only set the EOImode Bit to zero. > > refs: See Arm IHI 0069G, page 12-229. > > Signed-off-by: Zhiyuan Dai > --- > drivers/irqchip/irq-gic-v3.c | 9 +++++++-- > include/linux/irqchip/arm-gic-v3.h | 3 +-- > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index fd4e9a3..96466fc0 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -967,6 +967,7 @@ static void gic_cpu_sys_reg_init(void) > u64 need_rss = MPIDR_RS(mpidr); > bool group0; > u32 pribits; > + u32 val; > > /* > * Need to check that the SRE bit has actually been set. If > @@ -1009,12 +1010,16 @@ static void gic_cpu_sys_reg_init(void) > */ > gic_write_bpr1(0); > > + val = gic_read_ctlr(); > + > if (static_branch_likely(&supports_deactivate_key)) { > /* EOI drops priority only (mode 1) */ > - gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); > + val |= ICC_CTLR_EL1_EOImode; > + gic_write_ctlr(val); > } else { > /* EOI deactivates interrupt too (mode 0) */ > - gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); > + val &= ~ICC_CTLR_EL1_EOImode; > + gic_write_ctlr(val); I really wonder why you would need a read-modify-write sequence. There are no bits in ICC_CTLR_EL1 that we would want to preserve: - PHME: if it is writable, we really want it to be 0, as we don't use 1:N distribution - CBPR: We only use G1 interrupts, and we use ICC_BPR1_EL1 for preemption, hence the value being 0 All the other fields (apart from EOImode, obviously) are read-only or RES0, as per the architecture. Can you explain what you are trying to achieve here? Thanks, M. -- Without deviation from the norm, progress is not possible.