Re: [patch 1/8] PCI/MSI: Enable and mask MSIX early

[Thomas Gleixner <tglx@linutronix.de>]

On Wed, Jul 21 2021 at 14:38, Ashok Raj wrote:

> On Wed, Jul 21, 2021 at 09:11:27PM +0200, Thomas Gleixner wrote:
>> The ordering of MSI-X enable in hardware is disfunctional:
>> 
>>  1) MSI-X is disabled in the control register
>>  2) Various setup functions
>>  3) pci_msi_setup_msi_irqs() is invoked which ends up accessing
>>     the MSI-X table entries
>>  4) MSI-X is enabled and masked in the control register with the
>>     comment that enabling is required for some hardware to access
>>     the MSI-X table
>> 
>> #4 obviously contradicts #3. The history of this is an issue with the NIU
>> hardware. When #4 was introduced the table access actually happened in
>> msix_program_entries() which was invoked after enabling and masking MSI-X.
>> 
>> This was changed in commit d71d6432e105 ("PCI/MSI: Kill redundant call of
>> irq_set_msi_desc() for MSI-X interrupts") which removed the table write
>> from msix_program_entries().
>> 
>> Interestingly enough nobody noticed and either NIU still works or it did
>> not get any testing with a kernel 3.19 or later.
>> 
>> Nevertheless this is inconsistent and there is no reason why MSI-X can't be
>> enabled and masked in the control register early on, i.e. move #4 above to
>
> Does the above comment also apply to legacy MSI when it support per-vector
> masking capability? Probably not interesting since without IR, we only give
> 1 vector to MSI. 

No MSI is completely different as the MSI configuration is purely in PCI
config space while the MSI-X table is separately mapped.

Thanks,

        tglx