From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2831AC433ED for ; Thu, 20 May 2021 11:36:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08849611BD for ; Thu, 20 May 2021 11:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242101AbhETLhg (ORCPT ); Thu, 20 May 2021 07:37:36 -0400 Received: from mail.kernel.org ([198.145.29.99]:37990 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240513AbhETLRM (ORCPT ); Thu, 20 May 2021 07:17:12 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E512C61D6A; Thu, 20 May 2021 10:09:43 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ljfcb-002Ul9-16; Thu, 20 May 2021 11:09:41 +0100 Date: Thu, 20 May 2021 11:09:40 +0100 Message-ID: <8735uhvhqz.wl-maz@kernel.org> From: Marc Zyngier To: Steven Price Cc: Catalin Marinas , Will Deacon , James Morse , Julien Thierry , Suzuki K Poulose , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , Mark Rutland , Thomas Gleixner , qemu-devel@nongnu.org, Juan Quintela , "Dr. David Alan Gilbert" , Richard Henderson , Peter Maydell , Haibo Xu , Andrew Jones Subject: Re: [PATCH v12 6/8] arm64: kvm: Expose KVM_ARM_CAP_MTE In-Reply-To: <4e1fc7b7-ea8c-a87c-9177-d9e03ff96cb8@arm.com> References: <20210517123239.8025-1-steven.price@arm.com> <20210517123239.8025-7-steven.price@arm.com> <87tun1tg1l.wl-maz@kernel.org> <4e1fc7b7-ea8c-a87c-9177-d9e03ff96cb8@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: steven.price@arm.com, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave.Martin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, qemu-devel@nongnu.org, quintela@redhat.com, dgilbert@redhat.com, richard.henderson@linaro.org, peter.maydell@linaro.org, Haibo.Xu@arm.com, drjones@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 19 May 2021 14:26:31 +0100, Steven Price wrote: > > On 17/05/2021 18:40, Marc Zyngier wrote: > > On Mon, 17 May 2021 13:32:37 +0100, > > Steven Price wrote: > >> > >> It's now safe for the VMM to enable MTE in a guest, so expose the > >> capability to user space. > >> > >> Signed-off-by: Steven Price > >> --- > >> arch/arm64/kvm/arm.c | 9 +++++++++ > >> arch/arm64/kvm/sys_regs.c | 3 +++ > >> 2 files changed, 12 insertions(+) > >> > >> diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > >> index 1cb39c0803a4..e89a5e275e25 100644 > >> --- a/arch/arm64/kvm/arm.c > >> +++ b/arch/arm64/kvm/arm.c > >> @@ -93,6 +93,12 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, > >> r = 0; > >> kvm->arch.return_nisv_io_abort_to_user = true; > >> break; > >> + case KVM_CAP_ARM_MTE: > >> + if (!system_supports_mte() || kvm->created_vcpus) > >> + return -EINVAL; > >> + r = 0; > >> + kvm->arch.mte_enabled = true; > > > > As far as I can tell from the architecture, this isn't valid for a > > 32bit guest. > > Indeed, however the MTE flag is a property of the VM not of the vCPU. > And, unless I'm mistaken, it's technically possible to create a VM where > some CPUs are 32 bit and some 64 bit. Not that I can see much use of a > configuration like that. It looks that this is indeed a bug, and I'm on my way to squash it. Can't believe we allowed that for so long... But the architecture clearly states: These features are supported in AArch64 state only. So I'd expect something like: diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 956cdc240148..50635eacfa43 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -220,7 +220,8 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) switch (vcpu->arch.target) { default: if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { - if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) { + if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) || + vcpu->kvm->arch.mte_enabled) { ret = -EINVAL; goto out; } that makes it completely impossible to create 32bit CPUs within a MTE-enabled guest. Thanks, M. -- Without deviation from the norm, progress is not possible.