From: Andi Kleen <ak@linux.intel.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org,
Andrew Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [RFC PATCH, x86]: Disable CPA cache flush for selfsnoop targets
Date: Mon, 15 Jul 2019 09:31:05 -0700 [thread overview]
Message-ID: <8736j7gsza.fsf@linux.intel.com> (raw)
In-Reply-To: <CAFULd4b=5-=WfF9OPCX+H9VDnsgbN7OBFj-XP=MZ0QqF5WpvQA@mail.gmail.com> (Uros Bizjak's message of "Thu, 11 Jul 2019 10:12:55 +0200")
Uros Bizjak <ubizjak@gmail.com> writes:
> Recent patch [1] disabled a self-snoop feature on a list of processor
> models with a known errata, so we are confident that the feature
> should work on remaining models also for other purposes than to speed
> up MTRR programming.
MTRR is very different than TLBs.
From my understanding not flushing with PAT is only safe everywhere when
the memory is only used for coherent devices (like the Internal GPU on
Intel CPUs). We don't have any infrastructure to track or enforce
this unfortunately.
-Andi
next prev parent reply other threads:[~2019-07-15 16:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-11 8:12 [RFC PATCH, x86]: Disable CPA cache flush for selfsnoop targets Uros Bizjak
2019-07-11 14:39 ` Andy Lutomirski
2019-07-11 19:00 ` Uros Bizjak
2019-07-15 8:24 ` Thomas Gleixner
2019-07-15 12:04 ` Uros Bizjak
2019-07-15 16:31 ` Andi Kleen [this message]
2019-07-15 18:41 ` Thomas Gleixner
2019-07-15 19:19 ` Uros Bizjak
2019-07-15 19:30 ` Thomas Gleixner
2019-07-15 19:38 ` Andi Kleen
2019-07-15 22:12 ` Andy Lutomirski
2019-07-15 22:53 ` Andi Kleen
2019-07-15 23:10 ` Andy Lutomirski
2019-07-16 0:32 ` Andi Kleen
2019-07-15 19:39 ` Andi Kleen
2019-07-15 19:44 ` Andy Lutomirski
2019-07-15 19:46 ` Thomas Gleixner
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