From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AC703F86EC for ; Wed, 8 Jul 2026 17:20:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783531245; cv=none; b=gLWtEn0y+DiHdVaHFD4tyE1s/EBvQw6C9SJdzYWr4/OlprGlUzVV3XqLHDAbuHHwHMBOU19Q/yQpgBgNMxUe1xJwJEwxfo+S/A6SEu9YMyQXCRbAAHyj2Eadra2qM3HlM0xMo1/y0wlRQjprnUkJInFOcnviq4ZTFLwVDrFPXJw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783531245; c=relaxed/simple; bh=gWuwiivMSwqGA2u5Zr/9ovfo8yxcEyEwCqsWKEqpfBE=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=VAlUnVgXOn5JPWvi9dLn6McFShrni2HPGtRP5PJ4fITWVXPR5qzdXjY8hKYJJCLoLIr9GPB4Tg16znTzsnI5JjByREVXaOVljrPrUsc6l2tomJ1Zs91kM/6LIwdxIIxl5JqvzK8W+V8yla2h0FUlcOIT+dB5zdcKj10gZPlGJ40= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PT9Ab1c1; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=e1kvS8/Y; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PT9Ab1c1"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="e1kvS8/Y" From: Nam Cao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1783531240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JJ6OSb62+IgBxwwYG61LmV+eZUaWRn2nhO0DDPk2LNM=; b=PT9Ab1c12G2jSSIjgdIlHjiXJ76kZSEsz9oLw3ESSvFabGjsvlB8c/BiTBlYgyeEezfxbq vfhArQVI6OOBbIAjvhKbisZMxxgUFeT2PKRlO3b4nVsQr8OndnXkWu7ctFg3e3I5p9indO 5w8wD8SFUbLKVwCkjM/fqkAOtKsfWkVmFrEbiONUsGm3dMblkppSthXTYT+/t8pBdnhtnP gmIjJ44UcwBIQv1a27THywmkOuIrSilqpe1watYq+MMiUrUiWxvVMUCor2WX+CRIM9qg2F Y8qv1F9pTSsmXv9uUKKysNT7Sa2T7ITFBS5vbINuFKoAfZP/eNwB+ZrvW4L2/w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1783531240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JJ6OSb62+IgBxwwYG61LmV+eZUaWRn2nhO0DDPk2LNM=; b=e1kvS8/YnLXq6InSbpZ9GvpoOubkwZa3R9S2DxqdlkGm5ScWA5Py9kiPkURHuDIYBYSpXt 7nYSAYZHAWqX54Bw== To: =?utf-8?Q?Andr=C3=A9?= Almeida Cc: Alexandre Ghiti , Paul Walmsley , linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-riscv@lists.infradead.org, Albert Ou , Thomas =?utf-8?Q?Wei=C3=9Fschuh?= , Mathieu Desnoyers , Thomas Gleixner , Peter Zijlstra , Sebastian Andrzej Siewior , kernel-dev@igalia.com Subject: Re: [PATCH 5/5] riscv: vdso: Implement __vdso_futex_robust_try_unlock() In-Reply-To: <8d1bd8fb-1c35-4944-ab77-4dfc73ae5056@igalia.com> References: <7e567e288f9ddeb2128f5d7ed83a518945fb50d9.1781876501.git.namcao@linutronix.de> <8d1bd8fb-1c35-4944-ab77-4dfc73ae5056@igalia.com> Date: Wed, 08 Jul 2026 19:20:39 +0200 Message-ID: <874ii9pfdk.fsf@yellow.woof> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Andr=C3=A9 Almeida writes: > Hi Nam Cao, thanks for your patch! Hi, > How have you tested it? With a gdb breakpoint in the critical session. > I believe this is missing the ifdef header guard > > #ifndef __ASM_VDSO_FUTEX_H > #define __ASM_VDSO_FUTEX_H Right, thanks! >> +#if defined(CONFIG_RISCV_ISA_ZACAS) && defined(CONFIG_TOOLCHAIN_HAS_ZAC= AS) >> +#define FUTEX_CAS_OVERWRITE_VDSO_CS_RANGE(vdso, fd, idx, xlen, symbol) = \ >> +{ \ >> + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZACAS)) { \ >> + void *start =3D symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs= _cas_start));\ >> + void *end =3D symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs= _cas_end)); \ >> + \ >> + futex_set_vdso_cs_range(fd, idx, (uintptr_t)start, (uintptr_t)end, xl= en =3D=3D 32); \ >> + } \ >> +} >> +#else >> +#define FUTEX_CAS_OVERWRITE_VDSO_CS_RANGE(...) >> +#endif >> + >> +#define FUTEX_SET_VDSO_CS_RANGE(vdso, fd, idx, xlen, symbol) \ >> +{ \ >> + void *start =3D symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs_= lrsc_start)); \ >> + void *end =3D symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs_= lrsc_end)); \ >> + \ >> + futex_set_vdso_cs_range(fd, idx, (uintptr_t)start, (uintptr_t)end, xle= n =3D=3D 32); \ >> + \ >> + FUTEX_CAS_OVERWRITE_VDSO_CS_RANGE(vdso, fd, idx, xlen, symbol); \ >> + \ > > So if the build has support for CAS, the function overwrite what it had=20 > just set. Why do it even writes it in the first place then, can't this=20 > be an if/else? Functionally speaking, an if/else makes more sense. However, I cannot figure out how to do that without creating a complete mess, since *_try_unlock_cs_cas_start and *_try_unlock_cs_cas_end are not always available. If you have a suggestion, please do let me know. But doing it this way only costs us a few more instructions. Nam