[PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Icenowy Zheng]

This patchset tries to add support for Loongson 7A1000 PCH's LPC
interrupt controller to MIPS-based Loongson systems.

LPC, from software's perspective of view, is just ISA, so the interrupts
should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
machines handled it, the setup is fragile and depends on its specific
setup sequence (allocating the LPC IRQs first, and then allocate the
parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
breaks this fragile sequence, so the first two commits is created to
address this issue (by reserving ISA interrupts from the dynamic
allocation space).

Then the remaining commits are just adding OF(DT) based initialization
of PCH LPC interrupt controller, like what happened on PCH PIC.

Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
integrated ones.

Changes in v3:
- Override arch_dynirq_lower_bound() in MIPS Loongson64 / LoongArch
  instead of modifying the global version of function.
- Added Rob's R-b to the binding patch.

Changes in v2:
- Rebased on top of `irq-drivers-2026-02-09` tag.
- Compatible changed to `loongson,ls7a-lpc` .
- Merged the patch for conditionally build of ACPI code to the patch
  introducing OF code.
- Sorted function variable definitions.
- Reworded some commit messages as Thomas Glexiner suggests.
- Added __init to the LPC irqchip OF initialization code to prevent
  section mismatch.

Icenowy Zheng (8):
  MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs
  LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs
  dt-bindings: interrupt-controller: add LS7A PCH LPC
  irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init
  irqchip/loongson-pch-lpc: add OF init code
  irqchip/loongson-pch-lpc: enable building on MIPS Loongson64
  MIPS: Loongson64: dts: sort nodes
  MIPS: Loongson64: dts: add node for LS7A PCH LPC

 .../loongson,pch-lpc.yaml                     | 52 +++++++++++
 arch/loongarch/kernel/irq.c                   |  6 ++
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi     | 17 +++-
 arch/mips/loongson64/init.c                   |  6 ++
 drivers/irqchip/Kconfig                       |  1 -
 drivers/irqchip/irq-loongson-pch-lpc.c        | 87 ++++++++++++++-----
 6 files changed, 144 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

-- 
2.52.0

[PATCH v3 1/8] MIPS: Loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Icenowy Zheng]

On some Loongson 3A devices, a LPC bus is present and some legacy
devices (e.g. 8259) on it expect hardcoded low IRQ numbers. However
currently the expected low range IRQ numbers are not exempted from
the dynamic allocation, which leads to confliction when registering LPC
IRQs in the fixed range.

Override arch_dynirq_lower_bound() to reserve these low range IRQs and
prevent them from being dynamically allocated.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/loongson64/init.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5f73f8663ab2d..c7cc5a3d7817f 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -7,6 +7,7 @@
 #include <linux/irqchip.h>
 #include <linux/logic_pio.h>
 #include <linux/memblock.h>
+#include <linux/minmax.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <asm/bootinfo.h>
@@ -227,3 +228,8 @@ void __init arch_init_irq(void)
 	reserve_pio_range();
 	irqchip_init();
 }
+
+unsigned int arch_dynirq_lower_bound(unsigned int from)
+{
+	return MAX(from, NR_IRQS_LEGACY);
+}
-- 
2.52.0

[PATCH v3 2/8] LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Icenowy Zheng]

Loongson 7A PCH chips all contain a LPC controller, which is used in
some devices to connect legacy ISA devices (e.g. 8259 PS/2 controller).

The LPC IRQ driver will register LPC IRQs at the fixed range 0~15, and
the PCH PIC IRQ driver uses dynamic allocation. However the LPC IRQs are
currently not exempted from dynamic allocation.

The currently setup work by accident because the LPC IRQ controller is
the first consumer of PIC IRQ controller, and the PIC IRQ number is
allocated after LPC IRQs are registered. Such setup is fragile and will
stop to work when the LPC IRQ driver is reworked.

Override arch_dynirq_lower_bound() to reserve LPC IRQs from dynamic
allocation, to prevent IRQ number collision and allow rework of the LPC
IRQ driver.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/loongarch/kernel/irq.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 80946cafaec1b..7bf68a7a5f4b3 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -11,6 +11,7 @@
 #include <linux/irqchip.h>
 #include <linux/kernel_stat.h>
 #include <linux/proc_fs.h>
+#include <linux/minmax.h>
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/seq_file.h>
@@ -99,6 +100,11 @@ int __init arch_probe_nr_irqs(void)
 	return NR_IRQS_LEGACY;
 }
 
+unsigned int arch_dynirq_lower_bound(unsigned int from)
+{
+	return MAX(from, NR_IRQS_LEGACY);
+}
+
 void __init init_IRQ(void)
 {
 	int i;
-- 
2.52.0

[PATCH v3 3/8] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Icenowy Zheng]

Loongson 7A series PCH contains an LPC controller with an interrupt
controller.

Add the device tree binding for the interrupt controller.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
new file mode 100644
index 0000000000000..ff2a425b6f0b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCH LPC Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description:
+  This interrupt controller is found in the Loongson LS7A family of PCH for
+  accepting interrupts sent by LPC-connected peripherals and signalling PIC
+  via a single interrupt line when interrupts are available.
+
+properties:
+  compatible:
+    const: loongson,ls7a-lpc
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  '#interrupt-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - interrupts
+  - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    lpc: interrupt-controller@10002000 {
+      compatible = "loongson,ls7a-lpc";
+      reg = <0x10002000 0x400>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      interrupt-parent = <&pic>;
+      interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...
-- 
2.52.0

[PATCH v3 4/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init

[Icenowy Zheng]

A lot of code could be shared between the current ACPI init flow with
the possible OF init flow.

Extract it to a dedicated function.

The re-ordering of parent interrupt acquisition requires the
architecture code to reserve legacy interrupts from the dynamic
allocation by overriding arch_dynirq_lower_bound(), otherwise the parent
of LPC irqchip will be allocated to the intended static range of LPC
interrupts, which leads to allocation failure of LPC interrupts.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Yao Zi <me@ziyao.cc>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 52 ++++++++++++++++----------
 1 file changed, 32 insertions(+), 20 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 3ad46ec94e3c0..38d05135d2a7c 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -175,13 +175,10 @@ static struct syscore pch_lpc_syscore = {
 	.ops = &pch_lpc_syscore_ops,
 };
 
-int __init pch_lpc_acpi_init(struct irq_domain *parent,
-					struct acpi_madt_lpc_pic *acpi_pchlpc)
+static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
+			       struct fwnode_handle *irq_handle, int parent_irq)
 {
-	int parent_irq;
 	struct pch_lpc *priv;
-	struct irq_fwspec fwspec;
-	struct fwnode_handle *irq_handle;
 
 	priv = kzalloc_obj(*priv);
 	if (!priv)
@@ -189,7 +186,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	raw_spin_lock_init(&priv->lpc_lock);
 
-	priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
+	priv->base = ioremap(addr, size);
 	if (!priv->base)
 		goto free_priv;
 
@@ -198,12 +195,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 		goto iounmap_base;
 	}
 
-	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
-	if (!irq_handle) {
-		pr_err("Unable to allocate domain handle\n");
-		goto iounmap_base;
-	}
-
 	/*
 	 * The LPC interrupt controller is a legacy i8259-compatible device,
 	 * which requires a static 1:1 mapping for IRQs 0-15.
@@ -213,15 +204,10 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 						    &pch_lpc_domain_ops, priv);
 	if (!priv->lpc_domain) {
 		pr_err("Failed to create IRQ domain\n");
-		goto free_irq_handle;
+		goto iounmap_base;
 	}
 	pch_lpc_reset(priv);
 
-	fwspec.fwnode = parent->fwnode;
-	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
-	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
-	fwspec.param_count = 2;
-	parent_irq = irq_create_fwspec_mapping(&fwspec);
 	irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
 
 	pch_lpc_priv = priv;
@@ -230,8 +216,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return 0;
 
-free_irq_handle:
-	irq_domain_free_fwnode(irq_handle);
 iounmap_base:
 	iounmap(priv->base);
 free_priv:
@@ -239,3 +223,31 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return -ENOMEM;
 }
+
+int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc)
+{
+	struct fwnode_handle *irq_handle;
+	struct irq_fwspec fwspec;
+	int parent_irq, ret;
+
+	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
+	if (!irq_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		return -ENOMEM;
+	}
+
+	fwspec.fwnode = parent->fwnode;
+	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
+	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+	fwspec.param_count = 2;
+	parent_irq = irq_create_fwspec_mapping(&fwspec);
+
+	ret = pch_lpc_init(acpi_pchlpc->address, acpi_pchlpc->size,
+			   irq_handle, parent_irq);
+	if (ret) {
+		irq_domain_free_fwnode(irq_handle);
+		return ret;
+	}
+
+	return 0;
+}
-- 
2.52.0

[PATCH v3 5/8] irqchip/loongson-pch-lpc: add OF init code

[Icenowy Zheng]

The OF-based MIPS Loongson-3 systems can also have a PCH LPC interrupt
controller.

Add OF-based initialization code for this driver.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 35 ++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 38d05135d2a7c..a3d2c759f6a9d 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -13,6 +13,8 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/syscore_ops.h>
 
 #include "irq-loongson.h"
@@ -224,6 +226,7 @@ static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
 	return -ENOMEM;
 }
 
+#ifdef CONFIG_ACPI
 int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc)
 {
 	struct fwnode_handle *irq_handle;
@@ -251,3 +254,35 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic
 
 	return 0;
 }
+#endif /* CONFIG_ACPI */
+
+#ifdef CONFIG_OF
+static int __init pch_lpc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct fwnode_handle *irq_handle;
+	struct resource res;
+	int parent_irq, ret;
+
+	if (of_address_to_resource(node, 0, &res))
+		return -EINVAL;
+
+	parent_irq = irq_of_parse_and_map(node, 0);
+	if (!parent_irq) {
+		pr_err("Failed to get the parent IRQ for LPC IRQs\n");
+		return -EINVAL;
+	}
+
+	irq_handle = of_fwnode_handle(node);
+
+	ret = pch_lpc_init(res.start, resource_size(&res), irq_handle,
+			   parent_irq);
+	if (ret) {
+		irq_dispose_mapping(parent_irq);
+		return ret;
+	}
+
+	return 0;
+}
+
+IRQCHIP_DECLARE(pch_lpc, "loongson,ls7a-lpc", pch_lpc_of_init);
+#endif /* CONFIG_OF */
-- 
2.52.0

[PATCH v3 6/8] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64

[Icenowy Zheng]

As the driver can now support OF-based platforms, it's now possible to
use it on MIPS Loongson64 machines.

Drop the requirement of LOONGARCH for this driver, to allow build on
both MIPS-based and LoongArch-based Loongson systems.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f07b00d7fef90..f2eee2bd61dd0 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -761,7 +761,6 @@ config LOONGSON_PCH_MSI
 
 config LOONGSON_PCH_LPC
 	bool "Loongson PCH LPC Controller"
-	depends on LOONGARCH
 	depends on MACH_LOONGSON64 || LOONGARCH
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
-- 
2.52.0

[PATCH v3 7/8] MIPS: Loongson64: dts: sort nodes

[Icenowy Zheng]

The RTC's address is after UARTs, however the node is currently before
them.

Re-order the node to match address sequence.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index 6dee85909f5a6..59ca1ef0a7b64 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -19,13 +19,6 @@ pic: interrupt-controller@10000000 {
 			#interrupt-cells = <2>;
 		};
 
-		rtc0: rtc@100d0100 {
-			compatible = "loongson,ls7a-rtc";
-			reg = <0 0x100d0100 0 0x78>;
-			interrupt-parent = <&pic>;
-			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
 		ls7a_uart0: serial@10080000 {
 			compatible = "ns16550a";
 			reg = <0 0x10080000 0 0x100>;
@@ -65,6 +58,13 @@ ls7a_uart3: serial@10080300 {
 			no-loopback-test;
 		};
 
+		rtc0: rtc@100d0100 {
+			compatible = "loongson,ls7a-rtc";
+			reg = <0 0x100d0100 0 0x78>;
+			interrupt-parent = <&pic>;
+			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		pci@1a000000 {
 			compatible = "loongson,ls7a-pci";
 			device_type = "pci";
-- 
2.52.0

[PATCH v3 8/8] MIPS: Loongson64: dts: add node for LS7A PCH LPC

[Icenowy Zheng]

Loongson 7A series PCH contain a LPC IRQ controller.

Add the device tree node of it.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index 59ca1ef0a7b64..f304f99946f16 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -19,6 +19,15 @@ pic: interrupt-controller@10000000 {
 			#interrupt-cells = <2>;
 		};
 
+		lpc: interrupt-controller@10002000 {
+			compatible = "loongson,ls7a-lpc";
+			reg = <0 0x10002000 0 0x1000>;
+			interrupt-controller;
+			interrupt-parent = <&pic>;
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+		};
+
 		ls7a_uart0: serial@10080000 {
 			compatible = "ns16550a";
 			reg = <0 0x10080000 0 0x100>;
-- 
2.52.0

Re: [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Huacai Chen]

Hi, Icenowy,

On Sun, Mar 15, 2026 at 12:28 AM Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>
> This patchset tries to add support for Loongson 7A1000 PCH's LPC
> interrupt controller to MIPS-based Loongson systems.
>
> LPC, from software's perspective of view, is just ISA, so the interrupts
> should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
> Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
> machines handled it, the setup is fragile and depends on its specific
> setup sequence (allocating the LPC IRQs first, and then allocate the
> parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
> breaks this fragile sequence, so the first two commits is created to
> address this issue (by reserving ISA interrupts from the dynamic
> allocation space).
>
> Then the remaining commits are just adding OF(DT) based initialization
> of PCH LPC interrupt controller, like what happened on PCH PIC.
>
> Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
> integrated ones.
>
> Changes in v3:
> - Override arch_dynirq_lower_bound() in MIPS Loongson64 / LoongArch
>   instead of modifying the global version of function.
> - Added Rob's R-b to the binding patch.
>
> Changes in v2:
> - Rebased on top of `irq-drivers-2026-02-09` tag.
> - Compatible changed to `loongson,ls7a-lpc` .
> - Merged the patch for conditionally build of ACPI code to the patch
>   introducing OF code.
> - Sorted function variable definitions.
> - Reworded some commit messages as Thomas Glexiner suggests.
> - Added __init to the LPC irqchip OF initialization code to prevent
>   section mismatch.
>
> Icenowy Zheng (8):
>   MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs
>   LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs
Use upper case for the first word, which means....

>   dt-bindings: interrupt-controller: add LS7A PCH LPC
s/add/Add/g

>   irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init
s/extract/Extract/g

>   irqchip/loongson-pch-lpc: add OF init code
s/add/Add/g

>   irqchip/loongson-pch-lpc: enable building on MIPS Loongson64
s/enable/Enable/g

>   MIPS: Loongson64: dts: sort nodes
s/sort/Sort/g

>   MIPS: Loongson64: dts: add node for LS7A PCH LPC
s/add/Add/g

In addition, I think the last two patches should be in another series
because they won't go to the irqchip tree.

Huacai

>
>  .../loongson,pch-lpc.yaml                     | 52 +++++++++++
>  arch/loongarch/kernel/irq.c                   |  6 ++
>  arch/mips/boot/dts/loongson/ls7a-pch.dtsi     | 17 +++-
>  arch/mips/loongson64/init.c                   |  6 ++
>  drivers/irqchip/Kconfig                       |  1 -
>  drivers/irqchip/irq-loongson-pch-lpc.c        | 87 ++++++++++++++-----
>  6 files changed, 144 insertions(+), 25 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
>
> --
> 2.52.0
>

Re: [PATCH v3 1/8] MIPS: Loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Thomas Gleixner]

On Sun, Mar 15 2026 at 00:28, Icenowy Zheng wrote:
> On some Loongson 3A devices, a LPC bus is present and some legacy
> devices (e.g. 8259) on it expect hardcoded low IRQ numbers. However

s/IRQ/interrupt/ all over the place

Change log are supposed to be written in proper prose and not be riddled
with acronyms unless the acronym has a technical relevance like LPC or
ACPI. IRQ[s] does not qualify for that.

Thanks,

     tglx

Re: [PATCH v3 4/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init

[Thomas Gleixner]

On Sun, Mar 15 2026 at 00:28, Icenowy Zheng wrote:

> A lot of code could be shared between the current ACPI init flow with

s/could/can/    s/current/existing/

> the possible OF init flow.

s/possible/upcoming/

> Extract it to a dedicated function.

s/to/into/

> +
> +int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc)
> +{
> +	struct fwnode_handle *irq_handle;
> +	struct irq_fwspec fwspec;
> +	int parent_irq, ret;
> +
> +	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
> +	if (!irq_handle) {
> +		pr_err("Unable to allocate domain handle\n");
> +		return -ENOMEM;
> +	}
> +
> +	fwspec.fwnode = parent->fwnode;
> +	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
> +	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
> +	fwspec.param_count = 2;
> +	parent_irq = irq_create_fwspec_mapping(&fwspec);
> +
> +	ret = pch_lpc_init(acpi_pchlpc->address, acpi_pchlpc->size,
> +			   irq_handle, parent_irq);

No line break required. You have 100 characters per line.

Thanks,

        tglx

Re: [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Thomas Gleixner]

On Wed, Mar 18 2026 at 21:57, Huacai Chen wrote:
>>   MIPS: Loongson64: dts: sort nodes
> s/sort/Sort/g
>
>>   MIPS: Loongson64: dts: add node for LS7A PCH LPC
> s/add/Add/g
>
> In addition, I think the last two patches should be in another series
> because they won't go to the irqchip tree.

Correct.

Re: [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Icenowy Zheng]

在 2026-03-18三的 21:57 +0800，Huacai Chen写道：
> Hi, Icenowy,
> 
> On Sun, Mar 15, 2026 at 12:28 AM Icenowy Zheng
> <zhengxingda@iscas.ac.cn> wrote:
> > 
> > This patchset tries to add support for Loongson 7A1000 PCH's LPC
> > interrupt controller to MIPS-based Loongson systems.
> > 
> > LPC, from software's perspective of view, is just ISA, so the
> > interrupts
> > should be handled as legacy ones occupying the lowest 0-15 IRQ
> > numbers.
> > Despite the current PCH LPC driver for ACPI-based LoongArch
> > Loongson
> > machines handled it, the setup is fragile and depends on its
> > specific
> > setup sequence (allocating the LPC IRQs first, and then allocate
> > the
> > parent IRQ at PCH PIC). The refactor of extracting parent IRQ
> > allocation
> > breaks this fragile sequence, so the first two commits is created
> > to
> > address this issue (by reserving ISA interrupts from the dynamic
> > allocation space).
> > 
> > Then the remaining commits are just adding OF(DT) based
> > initialization
> > of PCH LPC interrupt controller, like what happened on PCH PIC.
> > 
> > Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse
> > as
> > integrated ones.
> > 
> > Changes in v3:
> > - Override arch_dynirq_lower_bound() in MIPS Loongson64 / LoongArch
> >   instead of modifying the global version of function.
> > - Added Rob's R-b to the binding patch.
> > 
> > Changes in v2:
> > - Rebased on top of `irq-drivers-2026-02-09` tag.
> > - Compatible changed to `loongson,ls7a-lpc` .
> > - Merged the patch for conditionally build of ACPI code to the
> > patch
> >   introducing OF code.
> > - Sorted function variable definitions.
> > - Reworded some commit messages as Thomas Glexiner suggests.
> > - Added __init to the LPC irqchip OF initialization code to prevent
> >   section mismatch.
> > 
> > Icenowy Zheng (8):
> >   MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC
> > IRQs
> >   LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs
> Use upper case for the first word, which means....

I'm going to change this for your preference, but please note that
there's no requirement of using upper case for `summary phrase` in the
Documentation/process/submitting-patches.rst document.

The examples in that document even include both examples with first
words being either upper case and lower case, which indicates both
should be acceptable:

```
Here are some good example Subjects::

    Subject: [PATCH 2/5] ext2: improve scalability of bitmap searching
    Subject: [PATCH v2 01/27] x86: fix eflags tracking
    Subject: [PATCH v2] sub/sys: Condensed patch summary
    Subject: [PATCH v2 M/N] sub/sys: Condensed patch summary
```

Thanks,
Icenowy

> 
> >   dt-bindings: interrupt-controller: add LS7A PCH LPC
> s/add/Add/g
> 
> >   irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI
> > init
> s/extract/Extract/g
> 
> >   irqchip/loongson-pch-lpc: add OF init code
> s/add/Add/g
> 
> >   irqchip/loongson-pch-lpc: enable building on MIPS Loongson64
> s/enable/Enable/g
> 
> >   MIPS: Loongson64: dts: sort nodes
> s/sort/Sort/g
> 
> >   MIPS: Loongson64: dts: add node for LS7A PCH LPC
> s/add/Add/g
> 
> In addition, I think the last two patches should be in another series
> because they won't go to the irqchip tree.
> 
> Huacai
> 
> > 
> >  .../loongson,pch-lpc.yaml                     | 52 +++++++++++
> >  arch/loongarch/kernel/irq.c                   |  6 ++
> >  arch/mips/boot/dts/loongson/ls7a-pch.dtsi     | 17 +++-
> >  arch/mips/loongson64/init.c                   |  6 ++
> >  drivers/irqchip/Kconfig                       |  1 -
> >  drivers/irqchip/irq-loongson-pch-lpc.c        | 87 ++++++++++++++-
> > ----
> >  6 files changed, 144 insertions(+), 25 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > 
> > --
> > 2.52.0
> > 

Re: [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Icenowy Zheng]

在 2026-03-20五的 10:16 +0100，Thomas Gleixner写道：
> On Wed, Mar 18 2026 at 21:57, Huacai Chen wrote:
> > >   MIPS: Loongson64: dts: sort nodes
> > s/sort/Sort/g
> > 
> > >   MIPS: Loongson64: dts: add node for LS7A PCH LPC
> > s/add/Add/g
> > 
> > In addition, I think the last two patches should be in another
> > series
> > because they won't go to the irqchip tree.
> 
> Correct.

To be honest, I don't know whether the first two patches should go to
the irqchip tree either; but the irqchip driver refactor depends on
these two patches.

Thanks,
Icenowy

Re: [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Thomas Gleixner]

On Sat, Mar 21 2026 at 16:59, Icenowy Zheng wrote:
> 在 2026-03-18三的 21:57 +0800，Huacai Chen写道：
> I'm going to change this for your preference, but please note that
> there's no requirement of using upper case for `summary phrase` in the
> Documentation/process/submitting-patches.rst document.

Interrupt chip code is maintained in the tip tree and that tree has a
supplementary document, which explicitely requests this:

  https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#patch-subject