[PATCH v2 0/2] PL353 SW ECC fixes

[PATCH v2 0/2] PL353 SW ECC fixes

[Andrea Scian via B4 Relay]

PL353 has some known errata with its ECC implementation and it may be
useful to switch to software ECC, to avoid issue with this.

On-die ECC is already supported (while I didn't test it) but when
enabling SW ECC we get operation-not-supported error during page write
(page read already work correctly)

IMHO it's enough to have 1-bit Hamming ECC correction, because this is
the only one supported on PL353, but this might be a wrong assumption.

This has been tested with nandflipbits and mtd_nandbiterrs

---
Changes in v2:
- change dev_info() into dev_dbg() to reduce messages
- Link to v1: https://lore.kernel.org/r/20260121-pl353-soft-ecc-support-v1-0-00ad8e160d83@dave.eu

---
Andrea Scian (2):
      mtd: rawnand: pl353: Fix software ECC support
      mtd: rawnand: pl353: Add message about ECC mode

 drivers/mtd/nand/raw/pl35x-nand-controller.c | 5 +++++
 1 file changed, 5 insertions(+)
---
base-commit: 24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7
change-id: 20260121-pl353-soft-ecc-support-794e1e75373a

Best regards,
-- 
Andrea Scian <andrea.scian@dave.eu>

[PATCH v2 1/2] mtd: rawnand: pl353: Fix software ECC support

[Andrea Scian via B4 Relay]

From: Andrea Scian <andrea.scian@dave.eu>

We need to set another couple of fields in ecc structure to allow
choosing SW ECC instead of HW one, otherwise write operation fail.

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
---
 drivers/mtd/nand/raw/pl35x-nand-controller.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c
index 11bd90e3f18cb..fcb62b9ec947b 100644
--- a/drivers/mtd/nand/raw/pl35x-nand-controller.c
+++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c
@@ -976,6 +976,8 @@ static int pl35x_nand_attach_chip(struct nand_chip *chip)
 		fallthrough;
 	case NAND_ECC_ENGINE_TYPE_NONE:
 	case NAND_ECC_ENGINE_TYPE_SOFT:
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+		chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
 		break;
 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
 		ret = pl35x_nand_init_hw_ecc_controller(nfc, chip);

-- 
2.43.0

Re: [PATCH v2 1/2] mtd: rawnand: pl353: Fix software ECC support

[Miquel Raynal]

Hello Andrea,

On 26/01/2026 at 17:58:55 +01, Andrea Scian via B4 Relay <devnull+andrea.scian.dave.eu@kernel.org> wrote:

> From: Andrea Scian <andrea.scian@dave.eu>
>
> We need to set another couple of fields in ecc structure to allow
> choosing SW ECC instead of HW one, otherwise write operation fail.

I'm not sure I captured in our previous exchanges that you were testing
with SW ECC.

> Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
> ---
>  drivers/mtd/nand/raw/pl35x-nand-controller.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c
> index 11bd90e3f18cb..fcb62b9ec947b 100644
> --- a/drivers/mtd/nand/raw/pl35x-nand-controller.c
> +++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c
> @@ -976,6 +976,8 @@ static int pl35x_nand_attach_chip(struct nand_chip *chip)
>  		fallthrough;
>  	case NAND_ECC_ENGINE_TYPE_NONE:
>  	case NAND_ECC_ENGINE_TYPE_SOFT:
> +		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;

This is unfortunately not relevant here. In software you can use
whatever algorithm you want. It is writeable in DT and should not be
hardcoded here. The only limit is the available OOB area for the
strength (depending on the NAND geometry).

> +		chip->ecc.write_page_raw = nand_monolithic_write_page_raw;

This, however, seems relevant and should be the oneliner!

Please add Cc: stable & Fixes tags to your v3.

Thanks,
Miquèl

[PATCH v2 2/2] mtd: rawnand: pl353: Add message about ECC mode

[Andrea Scian via B4 Relay]

From: Andrea Scian <andrea.scian@dave.eu>

This just add some information on kernel log about the selected ECC

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
---
 drivers/mtd/nand/raw/pl35x-nand-controller.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c
index fcb62b9ec947b..cbef4f0084844 100644
--- a/drivers/mtd/nand/raw/pl35x-nand-controller.c
+++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c
@@ -970,16 +970,19 @@ static int pl35x_nand_attach_chip(struct nand_chip *chip)
 
 	switch (chip->ecc.engine_type) {
 	case NAND_ECC_ENGINE_TYPE_ON_DIE:
+		dev_dbg(nfc->dev, "Using on-die ECC\n");
 		/* Keep these legacy BBT descriptors for ON_DIE situations */
 		chip->bbt_td = &bbt_main_descr;
 		chip->bbt_md = &bbt_mirror_descr;
 		fallthrough;
 	case NAND_ECC_ENGINE_TYPE_NONE:
 	case NAND_ECC_ENGINE_TYPE_SOFT:
+		dev_dbg(nfc->dev, "Using software ECC (Hamming 1-bit/512B)\n");
 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
 		chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
 		break;
 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
+		dev_dbg(nfc->dev, "Using hardware ECC\n");
 		ret = pl35x_nand_init_hw_ecc_controller(nfc, chip);
 		if (ret)
 			return ret;

-- 
2.43.0