From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB587C43334 for ; Wed, 20 Jul 2022 11:03:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238814AbiGTLDs (ORCPT ); Wed, 20 Jul 2022 07:03:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231272AbiGTLDq (ORCPT ); Wed, 20 Jul 2022 07:03:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B70926D9E9 for ; Wed, 20 Jul 2022 04:03:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5393261C11 for ; Wed, 20 Jul 2022 11:03:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2741C3411E; Wed, 20 Jul 2022 11:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658315024; bh=e3g0Eo75kOj/S29eu9i4MTaKxYID9Y95rqhSQSsymF8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=jEBi64d1FFvwWif7uDx+438UKq6slsk1TZSvC2WfEa2nk/M74zM8Zu7ppAiFdCjkr cJV0OEwgiNdKnGZO9Ao2gCX2xahcJ1SIolFa+qI60rZ8RUvAzFqPg7PMc/wqKef+DR jJs+r1E4oOvKB0BS1Yu/0oyjO6j5oV9jwoX0I58UAblSrwHw/nY+ashyi/rQOmGxSB feJAt0QX1X9nJgM1Q9WA5dUbHReowXwjUCm7XWNlHE0MJg8y/huqcHosB83LbHMl5K PvzMj2Y0cxf225v9ehkbis3YeqMwXNgYhdx25Eiu0a8/XPugXOE9cb38t9D0oJtGyu +5GJHFluwvA2Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oE7UU-008l2J-NI; Wed, 20 Jul 2022 12:03:42 +0100 Date: Wed, 20 Jul 2022 12:03:42 +0100 Message-ID: <874jzcyrjl.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V18 00/13] irqchip: Add LoongArch-related irqchip drivers In-Reply-To: <1658314292-35346-1-git-send-email-lvjianmin@loongson.cn> References: <1658314292-35346-1-git-send-email-lvjianmin@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 20 Jul 2022 11:51:19 +0100, Jianmin Lv wrote: > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > boot protocol LoongArch-specific interrupt controllers (similar to APIC) > are already added in the ACPI Specification 6.5(which may be published in > early June this year and the board is reviewing the draft). > > Currently, LoongArch based processors (e.g. Loongson-3A5000) can only > work together with LS7A chipsets. The irq chips in LoongArch computers > include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O > Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), PCH-PIC > (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller > in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). [...] OK, that's 4 versions in quick succession, so I suggest we stop the bikeshedding and focus on getting this actually merged. I'm going to stick this in a branch and throw it at -next. Any change will need to go on top of it, no rebasing. If anything that breaks cannot be fixed easily, I will drop the branch. Thanks, M. -- Without deviation from the norm, progress is not possible.