From: Marc Zyngier <maz@kernel.org>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: chenhuacai@kernel.org, kernel@xen0n.name, linux-kernel@vger.kernel.org
Subject: Re: [PATCH for-5.19 v2 2/2] loongarch: Mask out higher bits for cpuid and rename the function
Date: Fri, 10 Jun 2022 09:02:11 +0100 [thread overview]
Message-ID: <874k0t3q0s.wl-maz@kernel.org> (raw)
In-Reply-To: <20220609175242.977-2-jiaxun.yang@flygoat.com>
On Thu, 09 Jun 2022 18:52:42 +0100,
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> Only low 9 bits of CPUID CSR represents coreid, higher bits
> are marked as reserved. In case Loongson may define higher
> bits in future, just mask them out for get_csr_cpuid.
>
> Also, as we already have read_csr_cpuid, rename get_csr_cpuid
> to get_csr_coreid to reflect the actual bit domain name.
I assume you meant read_csr_cpuid here?
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> arch/loongarch/include/asm/loongarch.h | 4 ++--
> drivers/irqchip/irq-loongson-liointc.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 3ba4f7e87cd2..fe2408144fa3 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -1198,9 +1198,9 @@ static inline u64 drdtime(void)
> return val;
> }
>
> -static inline unsigned int get_csr_cpuid(void)
> +static inline unsigned int get_csr_coreid(void)
> {
> - return csr_read32(LOONGARCH_CSR_CPUID);
> + return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
> }
>
> static inline void csr_any_send(unsigned int addr, unsigned int data,
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 8d05d8bcf56f..2ee636b2d827 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -42,7 +42,7 @@
> #if defined(CONFIG_MIPS)
> #define liointc_core_id get_ebase_cpunum()
> #else
> -#define liointc_core_id get_csr_cpuid()
> +#define liointc_core_id read_csr_cpuid()
> #endif
>
> struct liointc_handler_data {
I'm not going to take this patch as part of 5.19, as loongarch doesn't
have any irqchip support yet, and this can be made part of the IRQ
enabling series if really necessary.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-06-10 8:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-09 17:52 [PATCH for-5.19 v2 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Jiaxun Yang
2022-06-09 17:52 ` [PATCH for-5.19 v2 2/2] loongarch: Mask out higher bits for cpuid and rename the function Jiaxun Yang
2022-06-10 8:02 ` Marc Zyngier [this message]
2022-06-10 8:04 ` [irqchip: irq/irqchip-fixes] irqchip/loongson-liointc: Use architecture register to get coreid irqchip-bot for Jiaxun Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=874k0t3q0s.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=chenhuacai@kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=kernel@xen0n.name \
--cc=linux-kernel@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox