Re: [PATCH RFC 1/2] x86/apic: Do not make an exception for PIC_CASCADE_IR when marking legacy irqs in irq_matrix

Thomas Gleixner
2021-03-17T21:19:36Z

On Wed, Mar 17 2021 at 21:14, Thomas Gleixner wrote:
> On Fri, Feb 19 2021 at 12:31, Vitaly Kuznetsov wrote:
> Even without looking at the machine I can tell you what's going on. MP
> config or ACPI has a pin assigned to IRQ 2 which I've not seen before.
> The code there is ignoring IRQ 2 because that's how the original code
> worked as well as it is reserved for the PIC_CASCADE_IRQ which should
> never fire and we actually want to catch an spurious interrupt on it.
>
> So depending on the overall configuration of that system and the
> resulting delivery modes this might be ok, but I'm really nervous about
> doing this wholesale as it might break old machines.
>
> Out of paranoia I'd rather ignore that IO/APIC pin completely if it
> claims to be IRQ2. I assume there is no device connected to it at all,
> right?

Seems at some point we lost the 'ignore cascade IRQ' logic in
IO/APIC. There is still a comment to that effect.

Let me do some archaeology.

Thanks,

tglx