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From: Marc Zyngier <maz@kernel.org>
To: Bjoern Doebel <doebel@amazon.de>
Cc: <stable@vger.kernel.org>, Thomas Gleixner <tglx@kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	David Woodhouse <dwmw@amazon.co.uk>,
	"Ali\ Saidi" <alisaidi@amazon.com>,
	David Arinzon <darinzon@amazon.com>,
	"Zeev\ Zilberman" <zeev@amazon.com>
Subject: Re: [PATCH] irqchip/gic-v3-its: Reconfigure ITS from software state on resume
Date: Wed, 08 Jul 2026 11:26:37 +0100	[thread overview]
Message-ID: <875x2p7p5u.wl-maz@kernel.org> (raw)
In-Reply-To: <akZPM6SeJiM8th0N@amazon.de>

On Thu, 02 Jul 2026 12:57:15 +0100,
Bjoern Doebel <doebel@amazon.de> wrote:
> 
> Hi all,
> 
> gentle ping on this one.
> 
> Since the original posting I've re-validated the fix against current
> mainline:
> 
>   - It still applies cleanly to v7.2-rc1 (and to v7.1.0).
> 
>   - I reproduced the original failure on *stock* v7.2-rc1. On EC2
>     Graviton instances, hibernation resume fails 100% of the time: the
>     ITS comes back reset, MAPD/MAPTI are never replayed, and the ENA
>     NIC silently loses its LPIs:
> 
>       ena 0000:00:05.0: ... didn't receive a MSI-X interrupt (cmd 3)
>       ena 0000:00:05.0: Failed to create IO CQ. error: -62
>

But how did the resumed kernel get there the first place? Surely you
had interrupts to load it, right?

>     The instance then has no networking after resume.
> 
>   - With this patch applied, the same kernel survives hibernate/resume
>     cleanly: 9/9 cycles with zero failures, across all three Graviton
>     generations (Graviton 2/3/4, i.e. Neoverse N1/V1/V2), networking
>     fully restored on every resume.
> 
> As described in the previous message, this is the fallout from 713335b6ee29
> ("irqchip/gic-v3-its: Implement .msi_teardown() callback"): device
> teardown no longer happens across a suspend/resume that keeps the MSI
> domain, so the ITS is never reprogrammed and drops interrupts after the
> hardware has been reset.
> 
> Could you take a look when you get a chance?

What I don't immediately see is how this particular patch influences
anything, given that at this point it isn't doing anything.

Beside that, how does hibernation actually influences LPIs being
released? Can you at least describe the sequence of events?

The other thing that worries me is that in general, (bare metal) GICv3
is unable to deal with hibernation, given that you can't reprogram the
property and pending table addresses. Yes, it *may* work if you are
lucky enough that the boot kernel and the resumed one use the same
memory regions, but this only show that you like playing Russian
roulette.

Thanks,

	M.

-- 
Jazz isn't dead. It just smells funny.

      parent reply	other threads:[~2026-07-08 10:24 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-07 18:31 [PATCH] irqchip/gic-v3-its: Reconfigure ITS from software state on resume Bjoern Doebel
2026-07-02 11:57 ` Bjoern Doebel
2026-07-02 15:13   ` Thomas Gleixner
2026-07-08 10:26   ` Marc Zyngier [this message]

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