Re: [RFC PATCH v2 10/12] spi: cadence-quadspi: implement PHY tuning algorithm

[Miquel Raynal <miquel.raynal@bootlin.com>]

On 13/01/2026 at 19:46:15 +0530, Santhosh Kumar K <s-k6@ti.com> wrote:

> Implement PHY tuning for SDR and DDR modes. PHY tuning calibrates RX
> and TX delay lines to find optimal timing for high-speed operation.
>
> Add DLL management functions:
> - cqspi_resync_dll(): Reset DLL and wait for lock
> - cqspi_set_dll(): Configure RX/TX delays (0-127)
>
> Add pre/post config functions that enable PHY mode during tuning and
> restore normal operation afterward. PHY mode consumes one dummy cycle,
> so adjust dummy count to maintain correct flash timing.
>
> SDR tuning uses 1D search across RX delays at fixed TX. Search for
> two valid windows at consecutive read_delay values, select the larger
> window, and use the midpoint.
>
> DDR tuning uses 2D search across RX and TX delays:
> - Primary and secondary RX boundary searches at different TX values
> - Binary search for gap boundaries within valid region
> - Temperature compensation with midpoint calculation
> - Systematic boundary searches using 4-step increments
>
> The DDR algorithm finds the four corners of the valid region, identifies
> gaps, calculates temperature-aware midpoints, and validates final settings.
>
> Signed-off-by: Santhosh Kumar K <s-k6@ti.com>

This commit is gold, thanks a lot for the details in the comments.

I have no authority on this part to acknowledge it formally, but I
believe this is great work. Looking forward to see it work in octal DTR
mode now ;-)

Thanks,
Miquèl