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bh=WHybtPrEE+zi5o3ljeKTwzS5wA2OXV70yRBDLljR35w=; b=C20eoSCK8YmsgFGWX7ymeJwf/cLoORxjYSJC+1tfnDfd6nDamJk+Oh94R6Anjcy5qeoT6K GpQS9iZYBRVH3/w7MegRlNwob+XJcbtO7+C9j75LwbdhYOnmZcecIyrdosCk6HTRIQly1p X9yX+5tVhSfetuDHT7VUtMQ1rgIXsQKHUO5tIZsV4KfTMiUw7yyLb+G71xEc9206GwwxE9 ZPydJJuV5LIca/fmpNOfmJPH8awDgwdEmk8mB/eiLu2sk/91cFUvLf7A5TMXLvzeUwvy7q kTx2+XKI0TnZHn/cfTSbO1sxUHAq0i14giWgkTTzTwCjuirjbfCfNqyge67hYw== From: Miquel Raynal To: Tudor Ambarus Cc: Richard Weinberger , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Michael Walle , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 19/19] mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips In-Reply-To: <05c0fc18-f50f-4f62-bc64-a297cbf927fd@linaro.org> (Tudor Ambarus's message of "Thu, 3 Apr 2025 11:13:36 +0100") References: <20250403-winbond-6-14-rc1-octal-v2-0-7846bd88fe83@bootlin.com> <20250403-winbond-6-14-rc1-octal-v2-19-7846bd88fe83@bootlin.com> <05c0fc18-f50f-4f62-bc64-a297cbf927fd@linaro.org> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Thu, 03 Apr 2025 12:35:51 +0200 Message-ID: <875xjl352w.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgddukeekfeefucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufgjfhgffffkgggtgfesthhqredttderjeenucfhrhhomhepofhiqhhuvghlucftrgihnhgrlhcuoehmihhquhgvlhdrrhgrhihnrghlsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeejgeeftdefledvieegvdejlefgleegjefhgfeuleevgfdtjeehudffhedvheegueenucffohhmrghinhepkhgvrhhnvghlrdhorhhgnecukfhppeelvddrudekgedruddutddrudelleenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeelvddrudekgedruddutddrudelledphhgvlhhopehlohgtrghlhhhoshhtpdhmrghilhhfrhhomhepmhhiqhhuvghlrdhrrgihnhgrlhessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepuddtpdhrtghpthhtohepthhuughorhdrrghmsggrrhhusheslhhinhgrrhhordhorhhgpdhrtghpthhtoheprhhitghhrghrugesnhhougdrrghtpdhrtghpthhtohepvhhighhnvghshhhrsehtihdrtghomhdprhgtphhtthhopehsqdhkieesthhirdgtohhmpdhrtghpthhtohepphhrrghthihushhhsehkvghrnhgvlhdrohhrghdprhgtphhtt hhopehmihgthhgrvghlseifrghllhgvrdgttgdprhgtphhtthhopehthhhomhgrshdrphgvthgriiiiohhnihessghoohhtlhhinhdrtghomhdprhgtphhtthhopehsthhlihhnvdesfihinhgsohhnugdrtghomh X-GND-Sasl: miquel.raynal@bootlin.com On 03/04/2025 at 11:13:36 +01, Tudor Ambarus wro= te: > Hi, Miquel, > > On 4/3/25 10:19 AM, Miquel Raynal wrote: >> These chips support single SPI, octal SPI and octal DDR SPI. >>=20 >> For now, only the SDR protocols are supported. >>=20 >> Tested with the W35N02JW variant, but the 04 one just has twice more >> dies and is described in the same datasheet, so we can reasonably expect >> that it will behave identically. >>=20 >> Reviewed-by: Tudor Ambarus >> Signed-off-by: Miquel Raynal > > Checked patches 15-19 now, I'm ok with them. When applying, please > substitute my Reviewed-by tag with Acked-by for patches from 7 to 21. > I explained why in the reply of v2 14/19. Thanks. Duly noted. I checked the b4 log, I don't understand why it picked your R-by tag on all these commits: $ b4 trailers -Su Finding code-review trailers for 22 commits... Checking change-id "20250214-winbond-6-14-rc1-octal-6f7db6be0204" Grabbing search results from lore.kernel.org Analyzing 52 code-review messages --- + Acked-by: Tudor Ambarus https://lore.kernel.org/all/cdc38266-18a9-4eff-bdad-c88b316310b3@linaro= .org + Reviewed-by: Tudor Ambarus https://lore.kernel.org/all/4d36e51f-323c-451c-afeb-a6e378e3ed53@linaro= .org --- Press Enter to apply these trailers or Ctrl-C to abort mtd: spinand: Use more specific naming for the (dual output) read from ca= che ops + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Use more specific naming for the (dual IO) read from cache = ops + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Use more specific naming for the (quad output) read from ca= che ops + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Use more specific naming for the (quad IO) read from cache = ops + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Use more specific naming for the program execution op + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Use more specific naming for the (single) program load op + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Use more specific naming for the (quad) program load op + Acked-by: Tudor Ambarus (=E2=9C=93 DKIM/li= naro.org) + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: winbond: Rename DTR variants + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: winbond: Add support for W35N01JW in single mode + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Define octal read from cache operations + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: winbond: Add octal read support + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: Define octal load to cache operations + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: winbond: Add octal program support + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips + Reviewed-by: Tudor Ambarus (=E2=9C=97 DKIM= /linaro.org) --- Invoking git-filter-repo to update trailers. New history written in 0.17 seconds... Completely finished after 0.38 seconds. Trailers updated. Thanks, Miqu=C3=A8l