From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68EEBC04FDF for ; Wed, 2 Aug 2023 15:58:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235482AbjHBP6i (ORCPT ); Wed, 2 Aug 2023 11:58:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235340AbjHBP6b (ORCPT ); Wed, 2 Aug 2023 11:58:31 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B454BA; Wed, 2 Aug 2023 08:58:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7D10E61A35; Wed, 2 Aug 2023 15:58:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D5C42C433C7; Wed, 2 Aug 2023 15:58:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690991908; bh=Efu/dr3jOn1VaTX57cLLSWiNYnjtaqySwrOSZDjUPqQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ZBXCXaWsYZ6ZlQct9rxxSKisWvEYggis2ghmHQxOrF9tMav+Gdntp6izvzlrlpDy/ 3rfy+IZKA07S0dDz4QSel+uFToUD58bYVI+A/Hsp9mE5NOGx+VIQ+nIiJL7YJedIQf GyhChNxbwFGapOZVy+M3mY32pow7Jaw/vMovuLQziwJ+1d9IPY/p9f5yksZ1kTieId NRWMw5FWyj+QAGevBlLdsE1hGaG1j6PIhQSlw8roYCbk/AoJYlZUcvcQllbw2Q8vAQ 9/jtQ2BpLI+ns2GEXvOQjqPkIwRtIFzPw9xIVYduJxEiSe/cOqo26To4TQ9K9txDeL gf6EGg97hnJ9A== Received: from [104.132.1.99] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qREF0-001Pz2-E9; Wed, 02 Aug 2023 16:58:26 +0100 Date: Wed, 02 Aug 2023 16:58:21 +0100 Message-ID: <875y5xqvvm.wl-maz@kernel.org> From: Marc Zyngier To: Raghavendra Rao Ananta Cc: Oliver Upton , James Morse , Suzuki K Poulose , Paolo Bonzini , Sean Christopherson , Huacai Chen , Zenghui Yu , Anup Patel , Atish Patra , Jing Zhang , Reiji Watanabe , Colton Lewis , David Matlack , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Catalin Marinas , Gavin Shan , Shaoqin Huang Subject: Re: [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range In-Reply-To: References: <20230722022251.3446223-1-rananta@google.com> <20230722022251.3446223-7-rananta@google.com> <87r0otr579.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 104.132.1.99 X-SA-Exim-Rcpt-To: rananta@google.com, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, seanjc@google.com, chenhuacai@kernel.org, yuzenghui@huawei.com, anup@brainfault.org, atishp@atishpatra.org, jingzhangos@google.com, reijiw@google.com, coltonlewis@google.com, dmatlack@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, catalin.marinas@arm.com, gshan@redhat.com, shahuang@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 31 Jul 2023 18:36:47 +0100, Raghavendra Rao Ananta wrote: >=20 > On Thu, Jul 27, 2023 at 3:58=E2=80=AFAM Marc Zyngier wro= te: > > > > On Sat, 22 Jul 2023 03:22:45 +0100, > > Raghavendra Rao Ananta wrote: > > > > > > Currently, the core TLB flush functionality of __flush_tlb_range() > > > hardcodes vae1is (and variants) for the flush operation. In the > > > upcoming patches, the KVM code reuses this core algorithm with > > > ipas2e1is for range based TLB invalidations based on the IPA. > > > Hence, extract the core flush functionality of __flush_tlb_range() > > > into its own macro that accepts an 'op' argument to pass any > > > TLBI operation, such that other callers (KVM) can benefit. > > > > > > No functional changes intended. > > > > > > Signed-off-by: Raghavendra Rao Ananta > > > Reviewed-by: Catalin Marinas > > > Reviewed-by: Gavin Shan > > > Reviewed-by: Shaoqin Huang > > > --- > > > arch/arm64/include/asm/tlbflush.h | 109 +++++++++++++++-------------= -- > > > 1 file changed, 56 insertions(+), 53 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/a= sm/tlbflush.h > > > index 412a3b9a3c25..f7fafba25add 100644 > > > --- a/arch/arm64/include/asm/tlbflush.h > > > +++ b/arch/arm64/include/asm/tlbflush.h > > > @@ -278,14 +278,62 @@ static inline void flush_tlb_page(struct vm_are= a_struct *vma, > > > */ > > > #define MAX_TLBI_OPS PTRS_PER_PTE > > > > > > +/* When the CPU does not support TLB range operations, flush the TLB > > > + * entries one by one at the granularity of 'stride'. If the TLB > > > + * range ops are supported, then: > > > > Comment format (the original was correct). > > > Isn't the format the same as original? Or are you referring to the > fact that it needs to be placed inside the macro definition? No, I'm referring to the multiline comment that starts with: /* When the CPU does not support TLB range operations... instead of the required: /* * When the CPU does not support TLB range operations which was correct before the coment was moved. Thanks, M. --=20 Without deviation from the norm, progress is not possible.