From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1296EC433E6 for ; Sat, 6 Mar 2021 18:31:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D8FF76501F for ; Sat, 6 Mar 2021 18:31:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231217AbhCFS26 (ORCPT ); Sat, 6 Mar 2021 13:28:58 -0500 Received: from mail.kernel.org ([198.145.29.99]:57020 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230311AbhCFS2Y (ORCPT ); Sat, 6 Mar 2021 13:28:24 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0561064F6E; Sat, 6 Mar 2021 18:28:24 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lIbf3-0005iN-Qy; Sat, 06 Mar 2021 18:28:21 +0000 Date: Sat, 06 Mar 2021 18:28:20 +0000 Message-ID: <875z24rvaz.wl-maz@kernel.org> From: Marc Zyngier To: Daniel Palmer Cc: Mark-PK Tsai , Daniel Palmer , Thomas Gleixner , Jason Cooper , Matthias Brugger , Linux Kernel Mailing List , linux-arm-kernel , linux-mediatek@lists.infradead.org, yj.chiang@mediatek.com Subject: Re: [PATCH] irqchip/irq-mst: Support polarity configuration In-Reply-To: References: <20210305120930.14297-1-mark-pk.tsai@mediatek.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: daniel@0x0f.com, mark-pk.tsai@mediatek.com, daniel@thingy.jp, tglx@linutronix.de, jason@lakedaemon.net, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, yj.chiang@mediatek.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 06 Mar 2021 17:06:51 +0000, Daniel Palmer wrote: > > Hi Mark-PK, > > I'm trying to understand the logic behind the changes. > It seems like the polarity of interrupts is always the same between > the MStar intc and the GIC? Low level interrupts are handled in the > mstar intc and become high level interrupts to the GIC? That's because the GIC only supports level-high input interrupts when they are level triggered (and rising edge when edge triggered). Thanks, M. -- Without deviation from the norm, progress is not possible.