Re: [PATCH v3 08/16] irqchip/gic: Configure SGIs as standard interrupts

Marc Zyngier
2020-09-14T16:48:35Z

Marek,

On 2020-09-14 14:26, Marek Szyprowski wrote:
> Hi Marc,
>
> On 14.09.2020 15:13, Marc Zyngier wrote:
>> On 2020-09-14 14:06, Marek Szyprowski wrote:
>>> On 01.09.2020 16:43, Marc Zyngier wrote:
>>>> Change the way we deal with GIC SGIs by turning them into proper
>>>> IRQs, and calling into the arch code to register the interrupt range
>>>> instead of a callback.
>>>>
>>>> Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
>>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>> This patch landed in linux next-20200914 as commit ac063232d4b0
>>> ("irqchip/gic: Configure SGIs as standard interrupts"). Sadly it
>>> breaks
>>> booting of all Samsung Exynos 4210/4412 based boards (dual/quad ARM
>>> Cortex A9 based). Here are the last lines from the bootlog:
>>>
>>> [    0.106322] CPU: Testing write buffer coherency: ok
>>> [    0.109895] CPU0: Spectre v2: using BPIALL workaround
>>> [    0.116057] CPU0: thread -1, cpu 0, socket 9, mpidr 80000900
>>> [    0.123885] Setting up static identity map for 0x40100000 -
>>> 0x40100060
>>> [    0.130191] rcu: Hierarchical SRCU implementation.
>>> [    0.137195] soc soc0: Exynos: CPU[EXYNOS4210] PRO_ID[0x43210211]
>>> REV[0x11] Detected
>>> [    0.145129] smp: Bringing up secondary CPUs ...
>>> [    0.156279] CPU1: thread -1, cpu 1, socket 9, mpidr 80000901
>>> [    0.156291] CPU1: Spectre v2: using BPIALL workaround
>>> [    2.716379] random: fast init done
>>
>> Thanks for the report. Is this the funky non-banked GIC?
>
> Both Exynos 4210 and 4412 use non-zero cpu-offset in GIC node in
> device-tree: arch/arm/boot/dts/exynos{4210,4412}.dtsi, so I assume that
> the GIC registers are not banked.

Annoyingly, it seems to work correctly in QEMU:

root@unassigned-hostname:~# cat /proc/interrupts
CPU0 CPU1
40: 0 0 GIC-0 89 Level mct_comp_irq
41: 16144 0 GIC-0 74 Level mct_tick0
42: 0 15205 GIC-0 80 Level mct_tick1
43: 0 0 COMBINER 18 Edge arm-pmu
44: 0 0 COMBINER 26 Edge arm-pmu
46: 2270 0 GIC-0 107 Level mmc0
48: 878 0 GIC-0 84 Level 13800000.serial
52: 0 0 GIC-0 90 Level 13860000.i2c
54: 0 0 GIC-0 67 Level 12680000.pdma
55: 0 0 GIC-0 68 Level 12690000.pdma
56: 0 0 GIC-0 66 Level 12850000.mdma
59: 0 0 COMBINER 45 Edge 13620000.sysmmu
60: 0 0 COMBINER 46 Edge 13630000.sysmmu
61: 0 0 COMBINER 44 Edge 12e20000.sysmmu
62: 0 0 COMBINER 34 Edge 11a20000.sysmmu
63: 0 0 COMBINER 35 Edge 11a30000.sysmmu
64: 0 0 COMBINER 36 Edge 11a40000.sysmmu
65: 0 0 COMBINER 37 Edge 11a50000.sysmmu
66: 0 0 COMBINER 38 Edge 11a60000.sysmmu
67: 0 0 COMBINER 40 Edge 12a30000.sysmmu
68: 0 0 COMBINER 42 Edge 11e20000.sysmmu
74: 0 0 GIC-0 79 Level 11400000.pinctrl
75: 0 0 GIC-0 78 Level 11000000.pinctrl
77: 0 0 COMBINER 39 Edge 12a20000.sysmmu
78: 0 0 COMBINER 43 Edge 12220000.sysmmu
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 32 63 Rescheduling interrupts
IPI3: 3925 5381 Function call interrupts
IPI4: 0 0 CPU stop interrupts
IPI5: 4375 3778 IRQ work interrupts
IPI6: 0 0 completion interrupts
Err: 0

Do you happen to know whether the QEMU emulation is trustworthy?

Thanks,

M.
--
Jazz is not dead. It just smells funny...