[RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Randy Li]

  At this stage it is the only "full features" and well verified 
USB EHCI controller in this platform. More review is always necessary.

Changelog:
 - v7:
    adding a wrapper for the reset operation for phy
    using that wrapper
 - v6:
    move pwms pinctrl to pwms node
    fix the order of the dtb file in Makefile
 - v5:
   - correct the mail format
 - v4:
   - re-order some nodes in alphabetical order
   - fix some minor bugs
   - add a entry in vendor list
 - v3:
   - fixing the rtc clock, using clock source from PMIC
   - enable the tmu
   - enable the fimc for elite board
   - suuport the audio codec at elite board
   - fixing minor bugs in the last commit
 - v2:
   - removing rtc node
     the clock source driver is not done yet.
   - adding exynos-bus
   - fixing the MFC

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
    wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
 drivers/phy/phy-core.c                               | 14 ++++++++++++++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 drivers/usb/dwc2/core_intr.c                         | 11 +++++++++++
 include/linux/phy/phy.h                              |  3 +++
 6 files changed, 55 insertions(+)

-- 
2.7.4

[RESEND PATCH v7 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 drivers/phy/phy-core.c  | 14 ++++++++++++++
 include/linux/phy/phy.h |  3 +++
 2 files changed, 17 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 8eca906..32e838d 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -357,6 +357,20 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode)
 }
 EXPORT_SYMBOL_GPL(phy_set_mode);
 
+int phy_reset(struct phy *phy)
+{
+	int ret;
+	if (!phy || !phy->ops->reset)
+		return 0;
+
+	mutex_lock(&phy->mutex);
+	ret = phy->ops->reset(phy);
+	mutex_unlock(&phy->mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phy_reset);
+
 /**
  * _of_phy_get() - lookup and obtain a reference to a phy by phandle
  * @np: device_node for which to get the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..7978df6 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
 	int	(*power_on)(struct phy *phy);
 	int	(*power_off)(struct phy *phy);
 	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
+	int	(*reset)(struct phy *phy);
 	struct module *owner;
 };
 
@@ -136,6 +138,7 @@ int phy_exit(struct phy *phy);
 int phy_power_on(struct phy *phy);
 int phy_power_off(struct phy *phy);
 int phy_set_mode(struct phy *phy, enum phy_mode mode);
+int phy_reset(struct phy *phy);
 static inline int phy_get_bus_width(struct phy *phy)
 {
 	return phy->attrs.bus_width;
-- 
2.7.4

Re: [RESEND PATCH v7 1/4] phy: Add reset callback

[Heiko Stuebner]

Hi Randy,

Am Samstag, 10. September 2016, 02:59:37 CEST schrieb Randy Li:
> The only use for this is for solving a hardware design problem in
> usb of Rockchip RK3288.
> 
> Signed-off-by: Randy Li <ayaka@soulik.info>

When sending new versions, please carry over received Reviewed- / Tested- / 
Acked-by tags received on old versions.

So again, to me this looks good.

Although Kishon suggested earlier to have the init callback do the reset and 
simply call it again in the reset-case, the whole refcounting done in phy_init 
and phy_exit (phy->init_count) really shows that init and exit should be 
called pairwise, so that extra reset callback seems justified, so from my phy-
noob-pov

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  drivers/phy/phy-core.c  | 14 ++++++++++++++
>  include/linux/phy/phy.h |  3 +++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index 8eca906..32e838d 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -357,6 +357,20 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode)
>  }
>  EXPORT_SYMBOL_GPL(phy_set_mode);
> 
> +int phy_reset(struct phy *phy)
> +{
> +	int ret;
> +	if (!phy || !phy->ops->reset)
> +		return 0;
> +
> +	mutex_lock(&phy->mutex);
> +	ret = phy->ops->reset(phy);
> +	mutex_unlock(&phy->mutex);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(phy_reset);
> +
>  /**
>   * _of_phy_get() - lookup and obtain a reference to a phy by phandle
>   * @np: device_node for which to get the phy
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index f08b672..7978df6 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -36,6 +36,7 @@ enum phy_mode {
>   * @power_on: powering on the phy
>   * @power_off: powering off the phy
>   * @set_mode: set the mode of the phy
> + * @reset: reseting the phy
>   * @owner: the module owner containing the ops
>   */
>  struct phy_ops {
> @@ -44,6 +45,7 @@ struct phy_ops {
>  	int	(*power_on)(struct phy *phy);
>  	int	(*power_off)(struct phy *phy);
>  	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
> +	int	(*reset)(struct phy *phy);
>  	struct module *owner;
>  };
> 
> @@ -136,6 +138,7 @@ int phy_exit(struct phy *phy);
>  int phy_power_on(struct phy *phy);
>  int phy_power_off(struct phy *phy);
>  int phy_set_mode(struct phy *phy, enum phy_mode mode);
> +int phy_reset(struct phy *phy);
>  static inline int phy_get_bus_width(struct phy *phy)
>  {
>  	return phy->attrs.bus_width;

[RESEND PATCH v7 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include <linux/reset.h>
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
+#include <linux/delay.h>
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
 	struct clk_hw	clk480m_hw;
 	struct phy	*phy;
 	bool		uart_enabled;
+	struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
 	return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+	if (phy->reset) {
+		reset_control_assert(phy->reset);
+		udelay(10);
+		reset_control_deassert(phy->reset);
+	}
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on	= rockchip_usb_phy_power_on,
 	.power_off	= rockchip_usb_phy_power_off,
+	.reset		= rockchip_usb_phy_reset,
 	.owner		= THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 		return -EINVAL;
 	}
 
+	rk_phy->reset = of_reset_control_get(child, "phy-reset");
+	if (IS_ERR(rk_phy->reset))
+		rk_phy->reset = NULL;
+
 	rk_phy->reg_offset = reg_offset;
 
 	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

Re: [RESEND PATCH v7 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Rob Herring]

On Sat, Sep 10, 2016 at 02:59:38AM +0800, Randy Li wrote:
> It is a hardware bug in RK3288, the only way to solve it is to
> reset the phy.
> 
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
>  .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
>  2 files changed, 23 insertions(+)

[RESEND PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..af27edc 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
 	int ret;
+	struct device_node *np = hsotg->dev->of_node;
 
 	/* Clear interrupt */
 	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 			/* Restart the Phy Clock */
 			pcgcctl &= ~PCGCTL_STOPPCLK;
 			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+			/*
+			 * It is a quirk in Rockchip RK3288, causing by
+			 * a hardware bug. This will propagate out and
+			 * eventually we'll re-enumerate the device.
+			 * Not great but the best we can do.
+			 */
+			if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+				phy_reset(hsotg->phy);
+
 			mod_timer(&hsotg->wkp_timer,
 				  jiffies + msecs_to_jiffies(71));
 		} else {
-- 
2.7.4

Re: [RESEND PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Sergei Shtylyov]

Hello.

On 09/09/2016 09:59 PM, Randy Li wrote:

> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
>
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
>
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
>
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
>  drivers/usb/dwc2/core_intr.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..af27edc 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
[...]
> @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  			/* Restart the Phy Clock */
>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +			/*
> +			 * It is a quirk in Rockchip RK3288, causing by

    Caused.

[...]

MBR, Sergei

Re: [RESEND PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2019 bytes --]

Hi Randy,

[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.8-rc5 next-20160909]
[cannot apply to phy/next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Randy-Li/the-fix-for-the-USB-HOST1-at-rk3288-platform/20160910-030348
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm-socfpga_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/usb/dwc2/core_intr.c: In function 'dwc2_handle_wakeup_detected_intr':
>> drivers/usb/dwc2/core_intr.c:391:5: error: implicit declaration of function 'phy_reset' [-Werror=implicit-function-declaration]
        phy_reset(hsotg->phy);
        ^
   cc1: some warnings being treated as errors

vim +/phy_reset +391 drivers/usb/dwc2/core_intr.c

   385				 * It is a quirk in Rockchip RK3288, causing by
   386				 * a hardware bug. This will propagate out and
   387				 * eventually we'll re-enumerate the device.
   388				 * Not great but the best we can do.
   389				 */
   390				if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
 > 391					phy_reset(hsotg->phy);
   392	
   393				mod_timer(&hsotg->wkp_timer,
   394					  jiffies + msecs_to_jiffies(71));

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 18471 bytes --]

[RESEND PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
 				clocks = <&cru SCLK_OTGPHY0>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBOTG_PHY>;
+				reset-names = "phy-reset";
 			};
 
 			usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
 				clocks = <&cru SCLK_OTGPHY2>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBHOST1_PHY>;
+				reset-names = "phy-reset";
 			};
 		};
 	};
-- 
2.7.4

Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Heiko Stuebner]

Hi Randy,

could you check if the other host-only dwc2 are also affected by this (rk3188, 
rk3036) please? Because they also seem to act up in some strange way 
sometimes.

Thanks
Heiko

Am Samstag, 10. September 2016, 02:59:36 CEST schrieb Randy Li:
>   At this stage it is the only "full features" and well verified
> USB EHCI controller in this platform. More review is always necessary.
>
> Changelog:
>  - v7:
>     adding a wrapper for the reset operation for phy
>     using that wrapper
>  - v6:
>     move pwms pinctrl to pwms node
>     fix the order of the dtb file in Makefile
>  - v5:
>    - correct the mail format
>  - v4:
>    - re-order some nodes in alphabetical order
>    - fix some minor bugs
>    - add a entry in vendor list
>  - v3:
>    - fixing the rtc clock, using clock source from PMIC
>    - enable the tmu
>    - enable the fimc for elite board
>    - suuport the audio codec at elite board
>    - fixing minor bugs in the last commit
>  - v2:
>    - removing rtc node
>      the clock source driver is not done yet.
>    - adding exynos-bus
>    - fixing the MFC
> 
> Randy Li (4):
>   phy: Add reset callback
>   phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
>     wakeup
>   usb: dwc2: assert phy reset when waking up in rk3288 platform
>   ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset
> 
>  .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
>  arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
>  drivers/phy/phy-core.c                               | 14 ++++++++++++++
>  drivers/phy/phy-rockchip-usb.c                       | 20
> ++++++++++++++++++++ drivers/usb/dwc2/core_intr.c                         |
> 11 +++++++++++ include/linux/phy/phy.h                              |  3
> +++
>  6 files changed, 55 insertions(+)

Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[ayaka]

On 09/13/2016 07:06 PM, Heiko Stuebner wrote:
> Hi Randy,
>
> could you check if the other host-only dwc2 are also affected by this (rk3188,
> rk3036) please? Because they also seem to act up in some strange way
But I don't have those board currently. I would arrange them anyway.
Btw, I would send a new version to correct the fault reported by the 
auto build machine.
> sometimes.
>
> Thanks
> Heiko
>
> Am Samstag, 10. September 2016, 02:59:36 CEST schrieb Randy Li:
>>    At this stage it is the only "full features" and well verified
>> USB EHCI controller in this platform. More review is always necessary.
>>
>> Changelog:
>>   - v7:
>>      adding a wrapper for the reset operation for phy
>>      using that wrapper
>>   - v6:
>>      move pwms pinctrl to pwms node
>>      fix the order of the dtb file in Makefile
>>   - v5:
>>     - correct the mail format
>>   - v4:
>>     - re-order some nodes in alphabetical order
>>     - fix some minor bugs
>>     - add a entry in vendor list
>>   - v3:
>>     - fixing the rtc clock, using clock source from PMIC
>>     - enable the tmu
>>     - enable the fimc for elite board
>>     - suuport the audio codec at elite board
>>     - fixing minor bugs in the last commit
>>   - v2:
>>     - removing rtc node
>>       the clock source driver is not done yet.
>>     - adding exynos-bus
>>     - fixing the MFC
>>
>> Randy Li (4):
>>    phy: Add reset callback
>>    phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
>>      wakeup
>>    usb: dwc2: assert phy reset when waking up in rk3288 platform
>>    ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset
>>
>>   .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
>>   arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
>>   drivers/phy/phy-core.c                               | 14 ++++++++++++++
>>   drivers/phy/phy-rockchip-usb.c                       | 20
>> ++++++++++++++++++++ drivers/usb/dwc2/core_intr.c                         |
>> 11 +++++++++++ include/linux/phy/phy.h                              |  3
>> +++
>>   6 files changed, 55 insertions(+)

Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Heiko Stuebner]

Am Dienstag, 13. September 2016, 19:26:03 CEST schrieb ayaka:
> On 09/13/2016 07:06 PM, Heiko Stuebner wrote:
> > Hi Randy,
> > 
> > could you check if the other host-only dwc2 are also affected by this
> > (rk3188, rk3036) please? Because they also seem to act up in some strange
> > way
> But I don't have those board currently. I would arrange them anyway.
> Btw, I would send a new version to correct the fault reported by the
> auto build machine.

What I meant was, if you could check with some hardware-people first, if the
other host-only dwc2 are supposedly also affected. Right now I'm trying to
determine if this effect is somehow related with the usb debounce issue
I'm seeing with some recent dwc2 patches [0].


Heiko

[0] http://lists.infradead.org/pipermail/linux-rockchip/2016-September/012141.html
https://git.kernel.org/cgit/linux/kernel/git/balbi/usb.git/commit/?h=testing/next&id=2938fc63e0c26bf694436ac81bc776c8b7eced0c