From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1156F23507B for ; Tue, 25 Aug 2026 07:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787642600; cv=none; b=m+KOZiwjIR1Ld9t2BEn3fY2rRjxZEFwPqgW6w3uD2onD/f7WmBdVUBxb55NUR5jw0IH0ibMXpulycpwfP69nm0LV4m+3ALy3xy4KfWms5ikN7Gm7/lzDwhlWVY61BQee5o5tFoGjOZypjS6NbD3TpaPEI2efOdw6RX2FmSVx1B4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787642600; c=relaxed/simple; bh=4yJb12wlsUuTqo3k3Mq5aZKKPICVJclxhkhANz/Jaf0=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Y1Ho/uV/bG8/UMy94+yPnjCE1dlkHq7BCTIthSiZBpuf3mcmltTzUyhqDFrmxvFA6roOp6/alX81xwpSDo+AK3QpkRxrF9OGOpVu8BC9CUSfTBabSyirnpC9FW3gTLSV326GglsFbE3STdzhjzBDAo7oodCAny+7PgCLlvNSHsU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mUbDLBAr; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mUbDLBAr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA1F81F000E9; Tue, 25 Aug 2026 07:23:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787642598; bh=eN5iHP6Z2JnvjXQlTAeAGoavA+UgNv+wdji4+NWzt4Q=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=mUbDLBArwrNd0qXn3nZbVYxXGmD+5yDJ4R1r+syOz0YwiwWCsBpvzGjEsLLwE1CsB R+1t+67zW7lo+aGzTwQFffdNpMKEJTVd2Mt60e4f/p5UaEsD/ipBvmi6krAm+XYONw ZO6VWNE/VyF9qXXsqhPm5GlH825SEGPBU9InTEjZYhPPZRt5wNHo46zKVPAtxy1e9V 5r+vCDZQrr/K85AlN7SbHq1m7DGOpaY9SHslWmkO4PwnNMVrY4LKYx0f6U9nyKNxUe Q6CvdBZAcHTYq57Baf4fJ0aM0dcm8USimlRJbdM+9v8hF3ZDacvpAsD3g9a3ex5aA3 q0jZCnmVh/fmA== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wylV6-00000000wOl-1TDx; Tue, 25 Aug 2026 07:23:16 +0000 Date: Tue, 25 Aug 2026 08:25:48 +0100 Message-ID: <877bleoe4j.wl-maz@kernel.org> From: Marc Zyngier To: Li Dou Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, radu@rendec.net, tglx@kernel.org Subject: Re: [PATCH] irqchip/gic-v3: Remove the ISB between AP0Rn and AP1Rn In-Reply-To: <20260825030454.1280-1-li8d6kernel@163.com> References: <87bjaro4th.wl-maz@kernel.org> <20260825030454.1280-1-li8d6kernel@163.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: li8d6kernel@163.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, radu@rendec.net, tglx@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 25 Aug 2026 04:04:54 +0100, Li Dou wrote: > > Hi Marc, > > On Mon, 24 Aug 2026 17:34:34 +0100, Marc Zyngier wrote: > >On Mon, 24 Aug 2026 03:34:03 +0100, > >Li Dou wrote: > >> > >> ARM GICv3 specification says(in section 4.8.4 "System register access to > >> the Active Priorities registers"): > >> > >> an ISB is not required between each write to ICC_AP0R_EL1, > >> Secure ICC_AP1R_EL1, and Non-secure ICC_AP1R_EL1. > >> > >> It means we can use one ISB after resetting AP0Rn and AP1Rn for context > >> synchronization. So just remove the previous one. > > > >I'm afraid you have misinterpreted the spec. > > > >Within each of the AP0Rn, Secure AP1Rn and Non-Secure AP1Rn classes, > >for any value of 'n', there is no need for any synchronisation. > > > >However, between classes, you absolutely need an ISB. And this is the > >reason why, just above the note you quote: > > > > > >Writes to these registers in any order other than the following can > >result in UNPREDICTABLE behavior: > > > >1. ICC_AP0R_EL1. > >2. Secure ICC_AP1R_EL1. > >3. Non-secure ICC_AP1R_EL1. > > > > > >While you can perfectly write each individual register of (1), (2) or > >(3) without any synchronisation, you absolutely must have a CSE > >*between* each of (1), (2) and (3). Linux being non-secure only, you > >only deal with (1) and (3), and you must have an ISB in between. > >Without it, reordering can happen and you end-up violating the above > >rule. > > The spec sometimes is overly convoluted. Thanks for the clarification. The spec is pretty clear in this particular case. It outlines the order by which group of registers must be written to, and therefore there is only one way to interpret the accompanying note. As for any spec, you need to read the whole thing, and not take a particular statement out of context. Thanks, M. -- Jazz isn't dead. It just smells funny.