From: Thomas Gleixner <tglx@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: Re: [PATCH v1 4/5] irqchip: starfive: Increase the interrupt source number up to 64
Date: Fri, 10 Apr 2026 16:37:02 +0200 [thread overview]
Message-ID: <877bqe286p.ffs@tglx> (raw)
In-Reply-To: <20260410090106.622781-5-changhuang.liang@starfivetech.com>
On Fri, Apr 10 2026 at 02:01, Changhuang Liang wrote:
> From: Mason Huo <mason.huo@starfivetech.com>
>
> StarFive JHB100 SoC interrupt controller actually supports 64 interrupt
> sources, the original code only supported up to 32. now it is extended
> to 64.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> drivers/irqchip/irq-starfive-jhb100-intc.c | 43 ++++++++++++++--------
> 1 file changed, 28 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/irq-starfive-jhb100-intc.c
> index 312a4634870a..d5ecbb603a58 100644
> --- a/drivers/irqchip/irq-starfive-jhb100-intc.c
> +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c
> @@ -18,10 +18,11 @@
> #include <linux/reset.h>
> #include <linux/spinlock.h>
>
> -#define STARFIVE_INTC_SRC0_CLEAR 0x10
> -#define STARFIVE_INTC_SRC0_MASK 0x14
> -#define STARFIVE_INTC_SRC0_INT 0x1c
> +#define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20))
> +#define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20))
> +#define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20))
>
> +#define STARFIVE_INTC_NUM 2
> #define STARFIVE_INTC_SRC_IRQ_NUM 32
>
> struct starfive_irq_chip {
> @@ -53,18 +54,26 @@ static void starfive_intc_bit_clear(struct starfive_irq_chip *irqc,
> static void starfive_intc_unmask(struct irq_data *d)
> {
> struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
> + int i, bitpos;
> +
> + i = d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM;
> + bitpos = d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM;
>
> raw_spin_lock(&irqc->lock);
> - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq));
> + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos));
> raw_spin_unlock(&irqc->lock);
> }
As you are touching this code, please convert the locking to guard()
guard(raw_spinlock)(&irqc->lock);
starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq));
> + for (i = 0; i < STARFIVE_INTC_NUM; i++) {
for (int i = 0; ...)
Thanks,
tglx
next prev parent reply other threads:[~2026-04-10 14:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-10 9:01 [PATCH v1 0/5] Add interrupt controller for JHB100 SoC Changhuang Liang
2026-04-10 9:01 ` [PATCH v1 1/5] dt-bindings: interrupt-controller: Convert the word "jh8100" to "jhb100" Changhuang Liang
2026-04-10 17:43 ` Conor Dooley
2026-04-10 9:01 ` [PATCH v1 2/5] irqchip: starfive: " Changhuang Liang
2026-04-10 14:26 ` Thomas Gleixner
2026-04-10 9:01 ` [PATCH v1 3/5] irqchip: starfive: Use devm_ interfaces to simplify resource release Changhuang Liang
2026-04-10 9:27 ` Philipp Zabel
2026-04-10 9:53 ` Changhuang Liang
2026-04-10 14:32 ` Thomas Gleixner
2026-04-10 9:01 ` [PATCH v1 4/5] irqchip: starfive: Increase the interrupt source number up to 64 Changhuang Liang
2026-04-10 14:37 ` Thomas Gleixner [this message]
2026-04-10 9:01 ` [PATCH v1 5/5] irqchip: starfive: Implement irq_set_type and irq_ack hooks Changhuang Liang
2026-04-10 14:46 ` Thomas Gleixner
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