Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

Krzysztof Kozlowski
2023-01-23T08:13:50Z

On 23/01/2023 08:32, Li Chen wrote:
> Add a Ambarella compatible.
>
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I8bcab3b763bdc7e400a04cc46589f0f694028a66
> ---
> .../bindings/pinctrl/ambarella,pinctrl.yaml | 160 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 161 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> new file mode 100644
> index 000000000000..51f5a9cc4714
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ambarella,pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella PIN controller
> +
> +maintainers:
> + - Li Chen <lchen@ambarella.org>
> +
> +description: |
> + The pins controlled by Ambarella SoC chip are organized in banks, each bank
> + has 32 pins. Each pin has at least 2 multiplexing functions, and generally,
> + the first function is GPIO.
> +
> + The PINCTRL node acts as a container for an arbitrary number of subnodes. And
> + these subnodes will fall into two categories.
> +
> + One is for GPIO, please see the "GPIO node" section for detail, and another one
> + is to set up a group of pins for a function, both pin configurations and mux
> + selection, and it's called group node in the binding document.
> +
> +properties:
> + compatible:
> + items:
> + - const: ambarella,pinctrl
> +
> + reg:
> + minItems: 4
> + maxItems: 4
> +

Same problems as with other patches. You need to fix all of my previous
comments.

Best regards,
Krzysztof