From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BF88C07E96 for ; Tue, 6 Jul 2021 13:06:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B69061C6D for ; Tue, 6 Jul 2021 13:06:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231407AbhGFNIp (ORCPT ); Tue, 6 Jul 2021 09:08:45 -0400 Received: from mail.kernel.org ([198.145.29.99]:59026 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231274AbhGFNIl (ORCPT ); Tue, 6 Jul 2021 09:08:41 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6F1E961C69; Tue, 6 Jul 2021 13:06:03 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m0km1-00Bjd3-FY; Tue, 06 Jul 2021 14:06:01 +0100 Date: Tue, 06 Jul 2021 14:06:01 +0100 Message-ID: <878s2j8udi.wl-maz@kernel.org> From: Marc Zyngier To: Huacai Chen Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Chen Zhu Subject: Re: [PATCH 2/9] irqchip/loongson-pch-pic: Improve edge triggered interrupt support In-Reply-To: <20210706030904.1411775-3-chenhuacai@loongson.cn> References: <20210706030904.1411775-1-chenhuacai@loongson.cn> <20210706030904.1411775-3-chenhuacai@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: chenhuacai@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, lixuefeng@loongson.cn, chenhuacai@gmail.com, jiaxun.yang@flygoat.com, zhuchen@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 06 Jul 2021 04:08:57 +0100, Huacai Chen wrote: > > Edge-triggered mode and level-triggered mode need different handlers, > and edge-triggered mode need a specific ack operation. So improve it. > Is this a fix? How does it work currently? > Signed-off-by: Chen Zhu > Signed-off-by: Huacai Chen > --- > drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c > index f790ca6d78aa..a4eb8a2181c7 100644 > --- a/drivers/irqchip/irq-loongson-pch-pic.c > +++ b/drivers/irqchip/irq-loongson-pch-pic.c > @@ -92,18 +92,22 @@ static int pch_pic_set_type(struct irq_data *d, unsigned int type) > case IRQ_TYPE_EDGE_RISING: > pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq); > pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq); > + irq_set_handler_locked(d, handle_edge_irq); > break; > case IRQ_TYPE_EDGE_FALLING: > pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq); > pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq); > + irq_set_handler_locked(d, handle_edge_irq); > break; > case IRQ_TYPE_LEVEL_HIGH: > pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq); > pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq); > + irq_set_handler_locked(d, handle_level_irq); > break; > case IRQ_TYPE_LEVEL_LOW: > pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq); > pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq); > + irq_set_handler_locked(d, handle_level_irq); You are changing the flow for the whole hierarchy. Are all the irqchips in the stack supporting this? > break; > default: > ret = -EINVAL; > @@ -113,11 +117,24 @@ static int pch_pic_set_type(struct irq_data *d, unsigned int type) > return ret; > } > > +static void pch_pic_ack_irq(struct irq_data *d) > +{ > + unsigned int reg; > + struct pch_pic *priv = irq_data_get_irq_chip_data(d); > + > + reg = readl(priv->base + PCH_PIC_EDGE + PIC_REG_IDX(d->hwirq) * 4); > + if (reg & BIT(PIC_REG_BIT(d->hwirq))) { > + writel(BIT(PIC_REG_BIT(d->hwirq)), > + priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4); > + } > + irq_chip_ack_parent(d); > +} > + > static struct irq_chip pch_pic_irq_chip = { > .name = "PCH PIC", > .irq_mask = pch_pic_mask_irq, > .irq_unmask = pch_pic_unmask_irq, > - .irq_ack = irq_chip_ack_parent, > + .irq_ack = pch_pic_ack_irq, > .irq_set_affinity = irq_chip_set_affinity_parent, > .irq_set_type = pch_pic_set_type, > }; Thanks, M. -- Without deviation from the norm, progress is not possible.