From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E96F382F1C for ; Wed, 1 Apr 2026 08:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775031058; cv=none; b=M82vq8Jp/ZYydayUm7WJpg6MxGUcDlHoEqGG5fVX6vpL7QABK0yyx4INfw87OKmpn6okY6UaGvd92NSaEIuTR4cHSKQ8J7pxNr6kUWG1sVO27CyPOu9kV3UiPaVO7T2miOhzBQF9BULEfFqfpO/SI7zEg4wCXin804WjicN6rkc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775031058; c=relaxed/simple; bh=YskfJw3NAcTlQbHlq9uT0BmPPBY9SAvyEdvrXoYW5rk=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=Ujlxb0eIolAfCrEzSU8QT4hisaVVxos+NVTFdjAfpO6dAl9K2CkLbelUZ9axLb7xXtrXbnX7YBWlLufsqc+ydA6AeMBBro0Qr45tu960mAeu9Tqwo72Ibk9d+o0Sf2k/0bQKF33vEv+9p/EuKcGV8hDiv8xmpd8AgJFotiRfIxc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=lXZ96rs0; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="lXZ96rs0" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 542CA1A3102; Wed, 1 Apr 2026 08:10:52 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 28B48602BF; Wed, 1 Apr 2026 08:10:52 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5BA61104502B1; Wed, 1 Apr 2026 10:10:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1775031051; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=A9ttN22Me+ZiZWu9p0P01wr6po3/qQojCjpmN8ArtYg=; b=lXZ96rs0fS4hs0EAzLG8IRQJud4DeY8QiwYhV+VBLAIR9QW/V26Zr/8Ky5RQhaJH7kXlT3 CajkWb/gnCk50dkelap+gRBIARvMMoCjAymMFv7xCw8TM1OYSY7z/4NEENRI2+Lko6ACW+ NWeg0iMvxtfCERIskY6X4uJmsmGPhcpVAaesn0gwLFJVhdoU9XaxvCknMz8JMMbF9AP3mA 4Vmfyb0hZcdtblTA4Dl/nXMxzhnz6iKrpUFAJ1X9AC+GFsyRE4hr7gsSfuUqhmLNVBx9Lg zuMk31c9bRPEzdjyZ4nI2as7a6wW66owYpzqVwreMvsgtOzAej+qzqvAudtprQ== From: Miquel Raynal To: Gabor Juhos Cc: Vinod Koul , Neil Armstrong , Igal Liberman , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH phy-fixes] phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register access In-Reply-To: <141b3528-f83a-4fc3-954f-630ce45e54df@gmail.com> (Gabor Juhos's message of "Wed, 1 Apr 2026 09:13:57 +0200") References: <20260321-a3700-utmi-fix-usb2_phy_ctrl-access-v1-1-6005ff4b5058@gmail.com> <87zf3o873b.fsf@bootlin.com> <141b3528-f83a-4fc3-954f-630ce45e54df@gmail.com> User-Agent: mu4e 1.12.7; emacs 30.2 Date: Wed, 01 Apr 2026 10:10:48 +0200 Message-ID: <87a4vn85iv.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 On 01/04/2026 at 09:13:57 +02, Gabor Juhos wrote: > Hi Miquel, > >> Hi Gabor, >>=20 >> On 21/03/2026 at 15:42:32 +01, Gabor Juhos wrote: >>=20 >>> The mvebu_a3700_utmi_phy_power_off() function tries to modify the >>> USB2_PHY_CTRL register by using the IO address of the PHY IP block along >>> with the readl/writel IO accessors. However, the register exist in the >>> USB miscellaneous register space, and as such it must be accessed via >>> regmap like it is done in the mvebu_a3700_utmi_phy_power_on() function. >>> >>> Change the code to use regmap_update_bits() for mod=C3=ADfying the regi= ster >>=20 >> Spurious accent here :-) ^ >>=20 >> Do you imply that the register access was not working? Or that it was >> not using the correct API? ... > > It was using the wrong API with wrong base address. > > The USB2_PHY_CTRL(x) macro gives back an offset relative to the base addr= ess of > the USB miscellaneous registers. However the current code uses that offse= t with > the base address of the UTMI PHY registers. > > So, instead of modifying the 'USB2 Host PHY Control' register at 0xd005f8= 04 it > changes the 'USB2 UTMI PHY PLL Control 1' register at 0xd005f004. Ok, that's what I was asking. > Since the miscellaneous registers can be accessed only via the regmap obt= ained > from a syscon node we have to use the regmap API instead of the generic IO > accessors. Yeah yeah, I was asking to clarify the problem, whether it was a register access issue or an API mismatch in the first place. >> ... (hence potential issues with locking might arise) > > The regmap API uses built-in locking so there should be no locking > issues. Yes, that's what I was implying, I was talking about the bare readl() call here (aka the "incorrect" API). Thanks, Miqu=C3=A8l