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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?l8FJX60Bc5O0tKmUSQIqmyLXBOzW7FrpOkxItvhotkMY0LbidjVmL21XuzXn?= =?us-ascii?Q?LPXu8ZR0JKD8UVAMy9R2dMfKDuie1hPlQN24p0LZPIGEXU+DTCf8WkvUKK61?= =?us-ascii?Q?J8554RdkkRhkPHJildTzR5U3t0MhHTP2DixD3oje+yBGwbReoKPKa7cug1za?= =?us-ascii?Q?MPbZNsog4FXYe66ppa0i0dlT2UaxeL5KcTJhI9pk4E/isj/TI4FJpJ5YaaM3?= =?us-ascii?Q?y0wik/Ps6W9tsUIfUWyZj0zjwwkpdwWpchz/JpiSESVb92v5ZC1i0i8p09Mm?= =?us-ascii?Q?n0VWgMnc0Ozak9JZWq7g+EHr4BZadiEV/j+/rLtDH4xXvuZeroHN1yPpf4z0?= =?us-ascii?Q?cIzA/jkn0Xy3q10zmVrO9EIlCmtHt7OF6RFiNmozQFqygsDbNYXZw8dmghm1?= =?us-ascii?Q?c2g+OnUPwsq/Mrc1MDfTgTDR035CBf6f01b9zLPiSsncSsRmqRiaXFXn9TrO?= =?us-ascii?Q?HXnibnZCp/DdgO4fJT4udvo1OOdA7hESbqwKURNMm8FSg15GlMhiuKo0gsUH?= =?us-ascii?Q?0J48SZW3/zD461qAcg2fAIP5/OX0t08MGBBXKR2ehfxpcUuTZ+OFOwJPltBy?= =?us-ascii?Q?4HQRzqFy+6KUVyv+jNtRPnJqLMDSqVImL+eKDUrUNoary8LBJgtUn8v4CMcN?= =?us-ascii?Q?SpsgfokG8uSkq2pO51/LGtvDpNzD0rYYvT32paC4E7wdbKduhrdDhxNMbY3y?= =?us-ascii?Q?Txapnf/pi+tYAXO70ERduefhhzQWFngn2At2CxsiTOrnR78eq20nwwtiQ5IN?= =?us-ascii?Q?bHxl177jmcRXrssl88cQowgNq/oluN36kOGJpA+0CuLuspTruUwGLeAULTKN?= =?us-ascii?Q?I9EepF38ZAxIPfgSfAZ4csoSam3Y1spKlI4RXPClpRK1BdOHEZyPG67GpUCa?= =?us-ascii?Q?h0ZkLMbJtvopSJ6V1qqn4XqdzjfG6/jdd+s9is2wD0Qf35f5x3Hi5MpBsbZL?= =?us-ascii?Q?A2sirIjUR4TVRzVbmRN4hLFz6fDnYObwf7D+B3E2qrBx/NcL+4e+PvrIi11H?= =?us-ascii?Q?ii8+C0Ld9Uz/XaWQsleDzduRmnkMcKibDY/ZnhtqU7bCvmzCDUdtmsN04xNA?= =?us-ascii?Q?Jcfh3JgJTdj189Dgwa79BtmUgJtpwTKTpehMjbY7JaNiultIc/dFyZkXxXBK?= =?us-ascii?Q?uNVaJZdBw8aHgkjWOr3zuNFzEK7voRET5CsLUIwMK+NBA1JVh4kx37CBEGGf?= =?us-ascii?Q?FDB9maGTFu6souJDLWzy4VFFZv0q1E76xoK/mr75bKQRKzr4CUyRfHtlfErP?= =?us-ascii?Q?KJuB2B3UQ4ZhYyvk+SYWT2jpxQQaL6s/pdbKsX/1i2tsgPSqKrPkmsMMg8g5?= =?us-ascii?Q?WxRzxaIKACZuqtb2nOaKTpZaI04joJcpvGdxnEDNzVJ0tKh2hYQmGpXG1jbW?= =?us-ascii?Q?StzNXPm2KYjSlQ0YSCs6X7Y0SQzo7SwaVsw5Zvwn4fQShkZ9VtUtb+KIlthP?= =?us-ascii?Q?9Hvf9g9ysz+o8N/ykdraKcOXYHi826qjSACFVEq0GSrz5l4LFU3LEoeW8e6E?= =?us-ascii?Q?Pj1GOCkTioiwgzbc3K34o6VvMt5RvGnd+gO4EzZ/xgdI9ZoP5tan1oKHXrZm?= =?us-ascii?Q?ruWHjOJUycCcG8VwymPo84NZx2p5l/r9EfJSGBL18Ws7zG/AkBSJl269yZgC?= =?us-ascii?Q?Hw=3D=3D?= X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: 27f1dfa3-ab23-4ec5-a776-08dd6bb2a37d X-MS-Exchange-CrossTenant-AuthSource: DB7PR10MB2475.EURPRD10.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2025 15:35:14.9455 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +Skgw/oxIikL5js4WhKV7caLAW5qHCf6aW1KcEMy1TX2MdTatbGHg8fzkxA3DNu9ueym5n3CqBjgY8qmkMnVK8BPMmJIRI/R3zWbf/j6aA8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR10MB3597 On Sat, Mar 22 2025, Colin Foster wrote: > On Thu, Mar 20, 2025 at 12:17:37PM +0100, Rasmus Villemoes wrote: >> Hi Colin >> >> On Wed, Mar 19 2025, Colin Foster wrote: >> >> > On Wed, Mar 19, 2025 at 01:30:53PM +0100, Rasmus Villemoes wrote: >> >> As the comments in ocelot-spi.c explain, after a chip reset, the >> >> CFGSTAT register must be written again setting the appropriate number >> >> of padding bytes; otherwise reads are not reliable. >> >> >> >> However, the way the code is currently structured violates that: After >> >> the BIT_SOFT_CHIP_RST is written, ocelot_chip_reset() immediately >> >> enters a readx_poll_timeout(). >> > >> > I ran this new version and everything worked - and I've not seen an >> > issue in previous versions. I'm looking for guidance as to whether this >> > should include a Fixes tag and be backported. >> >> Thanks a lot for testing and reviewing! As for backporting, IDK, I think >> we'd at least first have to know that it really fixes a bug for somebody. >> >> > Great find, by the way! Is there any information you would like from my >> > setup? >> >> Certainly I'd like to know if you do in fact use a SPI clock > 500 kHz? > > Yep, looks like 2.5MHz > > &spi0 { > #address-cells = <1>; > #size-cells = <0>; > status = "okay"; > > soc@0 { > compatible = "mscc,vsc7512"; > spi-max-frequency = <2500000>; > >> >> And if so, could you try inserting a read and printk of e.g. CHIP_REGS.CHIP_ID >> immediately after the fsleep(), but before the re-initialization, just >> so we can see if my theory that the values are off-by-8-bits plus 8 bits >> of MISO "garbage" is correct? Because that register should have a fairly >> easily recognizable value. > > diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c > index c00d30dbfca8..5a2762b6ecac 100644 > --- a/drivers/mfd/ocelot-core.c > +++ b/drivers/mfd/ocelot-core.c > @@ -115,6 +115,8 @@ static int ocelot_chip_reset(struct device *dev) > > if (ddata->init_bus) { > fsleep(VSC7512_GCB_RST_SLEEP_US); > + regmap_read(ddata->gcb_regmap, 0, &val); > + printk("7512 Chip ID after sleep: 0x%08x\n", val); > ret = ddata->init_bus(dev); > if (ret) > return dev_err_probe(dev, ret, > > > Prints out this: > > [ 3.360986] 7512 Chip ID after sleep: 0xf0e94051 > > That doesn't seem right. I added a print after init and it makes more sense. > > [ 3.351656] 7512 Chip ID after sleep: 0xf0e94051 > [ 3.356828] 7512 Chip ID after init: 0x175140e9 Thanks for testing. I hadn't realized that another thing the spi bus init does is setting the endianness, but this clearly shows both the off-by-one-byte and that the bytes are sent in the wrong order. It's hard to know how you end up with that f0 garbage byte, I'd assume either all-1s or all-0s when MISO is no longer driven explicitly. A wild guess could be that it's leftover capacitance (the last actually-driven bit is 1), which could explain why you haven't had a problem when reading the reset register and expected all zeroes, because in that case the device only sends 0s, and thus the garbage byte ends up also being a 0x00. So yes, it does seem like this warrants a backport. I'll add a Fixes tag for the next iteration, plus a link to this thread which demonstrates the problem. I suppose this goes back to f3e89362. Thanks, Rasmus