From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D13FC433EF for ; Fri, 19 Nov 2021 13:48:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7920561AEC for ; Fri, 19 Nov 2021 13:48:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235641AbhKSNvn (ORCPT ); Fri, 19 Nov 2021 08:51:43 -0500 Received: from mail.kernel.org ([198.145.29.99]:53728 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235580AbhKSNvh (ORCPT ); Fri, 19 Nov 2021 08:51:37 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3962861A02; Fri, 19 Nov 2021 13:48:36 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mo4Fl-006YTq-Ae; Fri, 19 Nov 2021 13:48:34 +0000 Date: Fri, 19 Nov 2021 13:48:32 +0000 Message-ID: <87a6i06ytr.wl-maz@kernel.org> From: Marc Zyngier To: Sai Prakash Ranjan Cc: Will Deacon , , Catalin Marinas , , , , , , , Subject: Re: [PATCHv4 2/2] arm64/io: Add a header for mmio access instrumentation In-Reply-To: <9396fbdc415a3096ab271868960372b21479e4fb.1636973694.git.quic_saipraka@quicinc.com> References: <9396fbdc415a3096ab271868960372b21479e4fb.1636973694.git.quic_saipraka@quicinc.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: quic_saipraka@quicinc.com, will@kernel.org, rostedt@goodmis.org, catalin.marinas@arm.com, quic_psodagud@quicinc.com, gregkh@linuxfoundation.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mingo@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 15 Nov 2021 11:33:30 +0000, Sai Prakash Ranjan wrote: > > The new generic header mmio-instrumented.h will keep arch code clean > and separate from instrumented version which traces mmio register > accesses. This instrumented header is generic and can be used by other > architectures as well. Also add a generic flag (__DISABLE_TRACE_MMIO__) > which is used to disable MMIO tracing in nVHE and if required can be > used to disable tracing for specific drivers. > > Signed-off-by: Sai Prakash Ranjan > --- > arch/arm64/include/asm/io.h | 25 ++++------- > arch/arm64/kvm/hyp/nvhe/Makefile | 2 +- > include/linux/mmio-instrumented.h | 70 +++++++++++++++++++++++++++++++ > 3 files changed, 80 insertions(+), 17 deletions(-) > create mode 100644 include/linux/mmio-instrumented.h > > diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h > index 7fd836bea7eb..a635aaaf81b9 100644 > --- a/arch/arm64/include/asm/io.h > +++ b/arch/arm64/include/asm/io.h > @@ -10,6 +10,7 @@ > > #include > #include > +#include > > #include > #include > @@ -21,32 +22,27 @@ > /* > * Generic IO read/write. These perform native-endian accesses. > */ > -#define __raw_writeb __raw_writeb > -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) > +static inline void arch_raw_writeb(u8 val, volatile void __iomem *addr) > { > asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_writew __raw_writew > -static inline void __raw_writew(u16 val, volatile void __iomem *addr) > +static inline void arch_raw_writew(u16 val, volatile void __iomem *addr) > { > asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_writel __raw_writel > -static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr) > +static __always_inline void arch_raw_writel(u32 val, volatile void __iomem *addr) > { > asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_writeq __raw_writeq > -static inline void __raw_writeq(u64 val, volatile void __iomem *addr) > +static inline void arch_raw_writeq(u64 val, volatile void __iomem *addr) > { > asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_readb __raw_readb > -static inline u8 __raw_readb(const volatile void __iomem *addr) > +static inline u8 arch_raw_readb(const volatile void __iomem *addr) > { > u8 val; > asm volatile(ALTERNATIVE("ldrb %w0, [%1]", > @@ -56,8 +52,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr) > return val; > } > > -#define __raw_readw __raw_readw > -static inline u16 __raw_readw(const volatile void __iomem *addr) > +static inline u16 arch_raw_readw(const volatile void __iomem *addr) > { > u16 val; > > @@ -68,8 +63,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr) > return val; > } > > -#define __raw_readl __raw_readl > -static __always_inline u32 __raw_readl(const volatile void __iomem *addr) > +static __always_inline u32 arch_raw_readl(const volatile void __iomem *addr) > { > u32 val; > asm volatile(ALTERNATIVE("ldr %w0, [%1]", > @@ -79,8 +73,7 @@ static __always_inline u32 __raw_readl(const volatile void __iomem *addr) > return val; > } > > -#define __raw_readq __raw_readq > -static inline u64 __raw_readq(const volatile void __iomem *addr) > +static inline u64 arch_raw_readq(const volatile void __iomem *addr) > { > u64 val; > asm volatile(ALTERNATIVE("ldr %0, [%1]", > diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile > index c3c11974fa3b..ff56d2165ea9 100644 > --- a/arch/arm64/kvm/hyp/nvhe/Makefile > +++ b/arch/arm64/kvm/hyp/nvhe/Makefile > @@ -4,7 +4,7 @@ > # > > asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS > -ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS > +ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__ > > hostprogs := gen-hyprel > HOST_EXTRACFLAGS += -I$(objtree)/include > diff --git a/include/linux/mmio-instrumented.h b/include/linux/mmio-instrumented.h > new file mode 100644 > index 000000000000..99979c025cc1 > --- /dev/null > +++ b/include/linux/mmio-instrumented.h > @@ -0,0 +1,70 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _LINUX_MMIO_INSTRUMENTED_H > +#define _LINUX_MMIO_INSTRUMENTED_H > + > +#include > + > +/* > + * Tracepoint and MMIO logging symbols should not be visible at EL2(HYP) as > + * there is no way to execute them and any such MMIO access from EL2 will > + * explode instantly (Words of Marc Zyngier). So introduce a generic flag > + * __DISABLE_TRACE_MMIO__ to disable MMIO tracing in nVHE and other drivers > + * if required. > + */ This Gospel would be better placed next to the code that defines the macro, given that this is an arch-independent include file, and hardly anyone understands the quirks of a nVHE KVM (and only nVHE, something that the comment fails to capture). M. -- Without deviation from the norm, progress is not possible.