Re: [PATCH v3 4/4] ARM: mvebu: prefix coprocessor operand with p

Gregory CLEMENT
2019-04-21T17:23:08Z

Hi Stefan,

> In every other instance where mrc is used the coprocessor operand
> is prefix with p (e.g. p15). Use the p prefix in this case too.
> This fixes a build issue when using LLVM's integrated assembler:
> arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for instruction
> mrc 15, 0, r3, cr0, cr0, 5
> ^
> arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
> mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
> ^
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> Acked-by: Nicolas Pitre <nico@fluxnic.net>

Applied on mvebu/arm, as well as the previous patch.

Thanks,

Gregory

> ---
> arch/arm/mach-mvebu/coherency_ll.S | 2 +-
> arch/arm/mach-mvebu/pmsu_ll.S | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
> index 8b2fbc8b6bc6..2d962fe48821 100644
> --- a/arch/arm/mach-mvebu/coherency_ll.S
> +++ b/arch/arm/mach-mvebu/coherency_ll.S
> @@ -66,7 +66,7 @@ ENDPROC(ll_get_coherency_base)
> * fabric registers
> */
> ENTRY(ll_get_coherency_cpumask)
> - mrc 15, 0, r3, cr0, cr0, 5
> + mrc p15, 0, r3, cr0, cr0, 5
> and r3, r3, #15
> mov r2, #(1 << 24)
> lsl r3, r2, r3
> diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
> index c1fb713e9306..7aae9a25cfeb 100644
> --- a/arch/arm/mach-mvebu/pmsu_ll.S
> +++ b/arch/arm/mach-mvebu/pmsu_ll.S
> @@ -16,7 +16,7 @@
> ENTRY(armada_38x_scu_power_up)
> mrc p15, 4, r1, c15, c0 @ get SCU base address
> orr r1, r1, #0x8 @ SCU CPU Power Status Register
> - mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
> + mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
> and r0, r0, #15
> add r1, r1, r0
> mov r0, #0x0
> --
> 2.21.0
>

--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering