From: Gregory CLEMENT <gregory.clement@free-electrons.com>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: robh+dt@kernel.org, bp@alien8.de, jlu@pengutronix.de,
linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH 0/4] EDAC: support reduce bus width on 98dx3236
Date: Wed, 20 Sep 2017 15:04:16 +0200 [thread overview]
Message-ID: <87a81pplm7.fsf@free-electrons.com> (raw)
In-Reply-To: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> (Chris Packham's message of "Mon, 7 Aug 2017 13:46:37 +1200")
Hi Chris,
On lun., août 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> (sorry I messed up sending this earlier, there is one additional patch and I'll
> actually include the linux-arm and linux-edac mailing lists)
>
> This series applies on top of Jan Lubbe's "EDAC drivers for Armada XP L2 and
> DDR" series[1]. 1/4, 2/4 and 3/4 don't strictly depend on Jan's work so they
> could go in through the ARM tree if that is preferred.
>
> The 98dx3236 and similar switch chips with integrated CPUs have fewer pins
> available for the SDRAM interface so the definition of "full" and "half" is
> different to the Armada-XP SoC. In this series I introduce a
> "marvell,reduced-width" device tree property and use this to identify such a
> system.
>
> I chose to use a new property instead of a new compatible string because the IP
> block really is the Armada-XP one (at least according to the Marvell FAE I
> spoke to) and because the scenario of requiring a reduced pin-count when going
> from an external SoC to an integrated one will be reasonably common as we see
> more an more of these switches with integrated ARM cores.
If I understood well a version 2 is expected. If I missed it, please
point me on it.
Once the binding will be acked I will be able to apply the dts
patch. For the first patch unless I am wrong the the series "EDAC
drivers for Armada XP L2 and DDR" was not applied or even formally
acked. Also while you will be at sending a new version please add a
commit log even a simple one.
For the 3rd patch, I also wait the new version of patch 2 with an
ack.
Thanks,
Gregory
>
>
> [1] - http://marc.info/?l=linux-edac&m=150167758312924
>
> Chris Packham (4):
> ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board
> dt-bindings: add "reduced-width" property for Armada XP SDRAM
> controller
> ARM: dts: mvebu: set reduced-width property for SDRAM on 98dx3236
> EDAC: add support for reduced-width Armada-XP SDRAM
>
> .../bindings/memory-controllers/mvebu-sdram-controller.txt | 6 ++++++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 1 +
> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
> drivers/edac/armada_xp_edac.c | 3 +++
> 4 files changed, 15 insertions(+)
>
> --
> 2.13.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2017-09-20 13:04 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-07 1:46 [RESEND PATCH 0/4] EDAC: support reduce bus width on 98dx3236 Chris Packham
2017-08-07 1:46 ` [RESEND PATCH 1/4] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board Chris Packham
2017-08-07 1:46 ` [RESEND PATCH 2/4] dt-bindings: add "reduced-width" property for Armada XP SDRAM controller Chris Packham
2017-08-10 20:38 ` Rob Herring
2017-08-10 21:17 ` Chris Packham
2017-08-11 9:34 ` Jan Lübbe
2017-08-07 1:46 ` [RESEND PATCH 3/4] ARM: dts: mvebu: set reduced-width property for SDRAM on 98dx3236 Chris Packham
2017-08-07 1:46 ` [RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM Chris Packham
2017-08-11 9:14 ` Borislav Petkov
2017-08-13 21:28 ` Chris Packham
2017-09-20 13:04 ` Gregory CLEMENT [this message]
2017-09-20 15:56 ` [RESEND PATCH 0/4] EDAC: support reduce bus width on 98dx3236 Chris Packham
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