From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754934AbcFGNEk (ORCPT ); Tue, 7 Jun 2016 09:04:40 -0400 Received: from mga04.intel.com ([192.55.52.120]:9112 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751500AbcFGNEj (ORCPT ); Tue, 7 Jun 2016 09:04:39 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,433,1459839600"; d="asc'?scan'208";a="117523211" From: Felipe Balbi To: Roger Quadros , Lu Baolu , Jun Li , Peter Chen Cc: Mathias Nyman , Greg Kroah-Hartman , Lee Jones , Heikki Krogerus , Liam Girdwood , Mark Brown , "linux-usb\@vger.kernel.org" , "linux-kernel\@vger.kernel.org" Subject: Re: [PATCH v10 2/7] usb: mux: add generic code for dual role port mux In-Reply-To: <5756C4DB.1050400@ti.com> References: <1464831449-8973-1-git-send-email-baolu.lu@linux.intel.com> <1464831449-8973-3-git-send-email-baolu.lu@linux.intel.com> <20160603074113.GA30006@shlinux2> <5751AAEE.2090001@linux.intel.com> <20160604022838.GA26936@shlinux2> <5753CCFC.2060504@linux.intel.com> <20160606012557.GA16012@shlinux2> <5754E850.1020707@linux.intel.com> <57552006.7080108@ti.com> <5756999B.9020809@linux.intel.com> <5756C4DB.1050400@ti.com> User-Agent: Notmuch/0.22+11~g124a67e (http://notmuchmail.org) Emacs/25.0.93.2 (x86_64-pc-linux-gnu) Date: Tue, 07 Jun 2016 16:04:27 +0300 Message-ID: <87a8ixb15w.fsf@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Hi, Roger Quadros writes: >> But you said I must run an unnecessary OTG state machine, even thought it >> has nothing to do with my system, only because the two sides of my port >> mux device is a host and peripheral controller. > > We have a minimal dual-role state machine that just looks at ID pin > and toggles the port role. I don't know if we want to bring all that extra baggage just to write a few bits in a single register. Even for DWC3-only dual-role (what Synopsys licenses as part of some DWC3 instantiations), the OTG/DRD layer is a bit overkill. If you take my testing/next, for example, we have everything we need for dual-role; except for OTG/DRD IRQ handler. Just look at how we implement =2D>suspend()/->resume() and it's be clear that we're just missing one step. I might be able to find some time to implement a proof of concept which would allow your platforms to get dual-role with code we already have, but I need DWC3's OTG support which, I'm assuming, you already have :-) If you wanna try something offline, just ping me ;-) I'll be happy to help. > How are you switching the port mux between host and peripheral? Only > by sysfs or do you have a GPIO for ID pin as well? depends. Some SoCs have GPIO-controller muxes while some just have mux's select signals (one for ID, one for VBUS) mapped on xHCI's address space. > What happens to the gadget controller when the port is muxed to the > host controller? Is it stopped or it continues to run? it continues running, but that's pretty irrelevant for Intel's dual-role setup. We have an actual physical (inside the die, though) mux which muxes USB signals to XHCI (not DWC3's XHCI) or to a peripheral-only DWC3. =2D-=20 balbi --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJXVsZbAAoJEIaOsuA1yqREjWsP/iVRG3QfNOkMvbRABvT03Puv 8MnIy6Cvm45Y08gl6+EtqItoBpyrKUgno9j44mILs4g/L90tmE5dLqTJ2nwcD0/a dWv1qLX1LQ/9GJM9EaR0GCSHfx2tqe0B8foQohdlRldkvO0SlYKRaHqBFkjO+ob0 mCqFRsPYFkoaFBNzgm0GAZOMNIlSqh3L81kSUth1IRp4uNqEQRknadqMHjIgJejF 77O5ibbh8sdrs80L5gYF+58Q0b1ZMkhQEmn/bpMLmqvNOTcovqbs63KvlfUyzmjO UbNkbTnG3anvrk6kOcPouyIRvFCVENK5ODYzTuFEAjWbwatWmLiTyaZ97PgthBOw EFC2c69iFIcDaxi7idCkXmdt8XMj8/JIkx4cKGmI5ep4UPLLNFTDsQtGR63umW3/ aAY5xEVRrbjn0B4Ib14kwAKLiDW642vlf2vX3uU9ZyEEzs2vLD58bnRTIQ0NkQB2 aDU/knzk+UT61cqAliWhLfk7zTeh5dU+VRMzGO1bYm41cvhEQjwVqq5gGQm1cKev zLkNi+n+tUXmdJ6OG9iCKFJUXrigkm1PC8LjEL6yUt2qCWzU6WjFgV/dj0FfCEQP Ma+KC7rZjlgC3YueMhd9VhsRvOeBcViA3gWIamcrJFKgduyQKntk0M0ovMPtn9df 0FSOYzGjKjmPD8jevRKp =Q+BF -----END PGP SIGNATURE----- --=-=-=--