From: Andi Kleen <andi@firstfloor.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@elte.hu>, LKML <linux-kernel@vger.kernel.org>,
Stephane Eranian <eranian@google.com>
Subject: Re: [PATCH] perf, x86: Add Nehelem PMU programming errata workaround
Date: Sat, 27 Mar 2010 22:27:55 +0100 [thread overview]
Message-ID: <87aattpi90.fsf@basil.nowhere.org> (raw)
In-Reply-To: <1269608924.12097.147.camel@laptop> (Peter Zijlstra's message of "Fri, 26 Mar 2010 14:08:44 +0100")
Peter Zijlstra <peterz@infradead.org> writes:
> Subject: perf, x86: Add Nehelem PMU programming errata workaround
> From: Peter Zijlstra <a.p.zijlstra@chello.nl>
> Date: Fri Mar 26 13:59:41 CET 2010
>
> Implement the workaround for Intel Errata AAK100 and AAP53.
>
> Also, remove the Core-i7 name for Nehalem events since there are also
> Westmere based i7 chips.
Did you actually see this happen?
It looks like this will make the context switch into a perf
enabled process _MUCH_ more expensive, MSR writes are very slow.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2010-03-27 21:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-26 13:08 [PATCH] perf, x86: Add Nehelem PMU programming errata workaround Peter Zijlstra
2010-03-26 14:33 ` [tip:perf/core] " tip-bot for Peter Zijlstra
2010-03-26 14:43 ` [PATCH] " Peter Zijlstra
2010-03-26 14:48 ` [tip:perf/core] " tip-bot for Peter Zijlstra
2010-03-27 21:27 ` Andi Kleen [this message]
2010-03-28 21:53 ` [PATCH] " Stephane Eranian
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