From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B4693C65E4 for ; Fri, 20 Mar 2026 15:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774019442; cv=none; b=CHoEl3qqYArGpvU0ApZEbXuztvsCA9sOOesfzd9ySybW+xvVRDoTB1zSsn3CtkuTI6MuRKmnhHrlLKEPm1E7ASXrDrjwhcvvhXWs9cvp5Kkoo83M/PSJG16nDdIisJnYH8fSN4iHvXeyQuSe0n3EpcOG0SQ1MRMdVhnW2K+rInw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774019442; c=relaxed/simple; bh=8NutCIg1nSzibPkpyDvrmrsAIlpHtcascMUrPpV4bFY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=cL98fCaKiissrSfFwyqROE7/nqGFl4HmGqQlffPXCv5jQqOCieNcLpYinPX6qL54CdAtMjvOrCC/OocHd6xKJ5rrKszgO2X/Y9fFC277U2PRY6eH4vwAAhpfw5CApKS1zGUgW7RWL1OFdv+v3CKusZnKwaYL3v5iAAZeOb3s3Yw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CqxyCRrX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CqxyCRrX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1F4FC2BC87; Fri, 20 Mar 2026 15:10:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774019441; bh=8NutCIg1nSzibPkpyDvrmrsAIlpHtcascMUrPpV4bFY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=CqxyCRrXEVdJ9Ua4Zk705ial7OG8sH6Y/jjG6sZL8eDkDnKLuxM5XABXmcwdnSyyo HtLl9uS+kB3yJSH8a3PDfmkesHwsfOX3yb9zbCp+OD4YEv08fmVtLPCL8F1KWH/mD2 pprI+FSZvUcYYdGi6UTz9pkGMo6sN07rj3tniOS1HlWsG3VnE4gEz/7VZ8k7wGC6v9 iXT7Vq8dpG3HFY+sGc5QbEtOvaEswARLM0647As2XKqwklViOY3/T7G5zDpRLlJrSh uWkZJKLAOV52AlrRSEaETGe6UGaXTsT5LXX1hqAyMp2RokqCdLatDi0pVWIiYDHW37 zR7jd+qnRg5yQ== From: Thomas Gleixner To: Michael Kelley , Marc Zyngier , Lorenzo Pieralisi , "linux-arm-kernel@lists.infradead.org" , LKML Cc: Sebastian Andrzej Siewior , Jan Kiszka Subject: Re: Question: interrupt randomness and handle_percpu_devid_irq() In-Reply-To: References: Date: Fri, 20 Mar 2026 16:10:37 +0100 Message-ID: <87bjgik042.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu, Mar 19 2026 at 19:34, Michael Kelley wrote: > The function header comment for handle_percpu_devid_irq() says that it is the > same as handle_percpu_irq(), but with the addition of a pointer to a percpu > variable with the real device id. That makes sense. But there's another difference: > handle_percpu_irq() calls add_interrupt_randomness() [via handle_irq_event_percpu()], > while handle_percpu_devid_irq() does not. > > Question: Is there a reason for this difference in handling interrupt randomness? > Or is it just an oversight? handle_percpu_devid_irq() is used, for example, for the > SGIs and PPIs on the GICv3 chip, so I wondered if IPIs (as built on SGIs) & PPIs > specifically did not want the overhead of add_interrupt_randomness(). But then > GICv5 is doing IPIs using LPIs, which use handle_percpu_irq() and hence *do* > add interrupt randomness. That seemed inconsistent, which didn't help provide > an answer. > > The question arises in the context of Linux guests running on Hyper-V. Hyper-V > VMBus interrupts to the guest are per-CPU interrupts in Linux, using a PPI on > arm64. So these interrupts do not call add_interrupt_randomness(), which is a > problem because these guests don't have much other way to get entropy. To > fix this, the VMBus ISR has always had an explicit call to > add_interrupt_randomness(). But maybe that's not the best approach, and > handle_percpu_devid_irq() should be fixed to call add_interrupt_randomness(). I don't think there is a real good reason unless any of those interrupts is NMI like. Thanks, tglx