[PATCH v3 0/9] Add RZ/G3L IRQC support

[PATCH v3 0/9] Add RZ/G3L IRQC support

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The IRQC block on RZ/G3L SoC is almost identical to one found on the
RZ/G3S SoC with the difference like it support more External IRQs, GPT
Error Interrupts and also has additional registers for GPT/MTU IRQ
selection, shared IRQ selection between external IRQ and TINT.

It has 16 external interrupts of which 8 interrupts are shared with
TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
selection is based on a register in the ICU block.

v2->v3:
 * Dropped items and instead used enum for single compatible values
 * Add minItems for interrupts and interrupt-names properties of 
   the RZ/{G2L,G2UL,Five,V2L} SoCs
 * Replaced maxItems->minItems for interrupts and interrupt-names
   properties of the RZ/G3L SoC.
v1->v2:
 * Simplified the binding by using pattern for intterrupt-names
 * Fixed the binding warnings reported by bot.

Biju Das (9):
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for
    interrupt-names
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L
    SoC
  irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct
    rzg2l_irqc_priv
  irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
  irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
  irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
  irqchip/renesas-rzg2l: Add RZ/G3L support
  irqchip/renesas-rzg2l: Add shared irq support
  arm64: dts: renesas: r9a08g046: Add ICU node

 .../renesas,rzg2l-irqc.yaml                   | 157 +++++--------
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    |  91 ++++++++
 drivers/irqchip/irq-renesas-rzg2l.c           | 218 +++++++++++++++---
 3 files changed, 337 insertions(+), 129 deletions(-)

-- 
2.43.0

[PATCH v3 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Simplify the bindings by using pattern property for interrupt-names.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * New patch.
---
 .../renesas,rzg2l-irqc.yaml                   | 120 ++++--------------
 1 file changed, 23 insertions(+), 97 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 44b6ae5fc802..a0b57d808639 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -48,107 +48,33 @@ properties:
 
   interrupts:
     minItems: 45
-    items:
-      - description: NMI interrupt
-      - description: IRQ0 interrupt
-      - description: IRQ1 interrupt
-      - description: IRQ2 interrupt
-      - description: IRQ3 interrupt
-      - description: IRQ4 interrupt
-      - description: IRQ5 interrupt
-      - description: IRQ6 interrupt
-      - description: IRQ7 interrupt
-      - description: GPIO interrupt, TINT0
-      - description: GPIO interrupt, TINT1
-      - description: GPIO interrupt, TINT2
-      - description: GPIO interrupt, TINT3
-      - description: GPIO interrupt, TINT4
-      - description: GPIO interrupt, TINT5
-      - description: GPIO interrupt, TINT6
-      - description: GPIO interrupt, TINT7
-      - description: GPIO interrupt, TINT8
-      - description: GPIO interrupt, TINT9
-      - description: GPIO interrupt, TINT10
-      - description: GPIO interrupt, TINT11
-      - description: GPIO interrupt, TINT12
-      - description: GPIO interrupt, TINT13
-      - description: GPIO interrupt, TINT14
-      - description: GPIO interrupt, TINT15
-      - description: GPIO interrupt, TINT16
-      - description: GPIO interrupt, TINT17
-      - description: GPIO interrupt, TINT18
-      - description: GPIO interrupt, TINT19
-      - description: GPIO interrupt, TINT20
-      - description: GPIO interrupt, TINT21
-      - description: GPIO interrupt, TINT22
-      - description: GPIO interrupt, TINT23
-      - description: GPIO interrupt, TINT24
-      - description: GPIO interrupt, TINT25
-      - description: GPIO interrupt, TINT26
-      - description: GPIO interrupt, TINT27
-      - description: GPIO interrupt, TINT28
-      - description: GPIO interrupt, TINT29
-      - description: GPIO interrupt, TINT30
-      - description: GPIO interrupt, TINT31
-      - description: Bus error interrupt
-      - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
-      - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
-      - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
-      - description: ECCRAM1 1bit error interrupt
-      - description: ECCRAM1 2bit error interrupt
-      - description: ECCRAM1 error overflow interrupt
+    maxItems: 48
 
   interrupt-names:
     minItems: 45
+    maxItems: 48
     items:
-      - const: nmi
-      - const: irq0
-      - const: irq1
-      - const: irq2
-      - const: irq3
-      - const: irq4
-      - const: irq5
-      - const: irq6
-      - const: irq7
-      - const: tint0
-      - const: tint1
-      - const: tint2
-      - const: tint3
-      - const: tint4
-      - const: tint5
-      - const: tint6
-      - const: tint7
-      - const: tint8
-      - const: tint9
-      - const: tint10
-      - const: tint11
-      - const: tint12
-      - const: tint13
-      - const: tint14
-      - const: tint15
-      - const: tint16
-      - const: tint17
-      - const: tint18
-      - const: tint19
-      - const: tint20
-      - const: tint21
-      - const: tint22
-      - const: tint23
-      - const: tint24
-      - const: tint25
-      - const: tint26
-      - const: tint27
-      - const: tint28
-      - const: tint29
-      - const: tint30
-      - const: tint31
-      - const: bus-err
-      - const: ec7tie1-0
-      - const: ec7tie2-0
-      - const: ec7tiovf-0
-      - const: ec7tie1-1
-      - const: ec7tie2-1
-      - const: ec7tiovf-1
+      oneOf:
+        - description: NMI interrupt
+          const: nmi
+        - description: External IRQ interrupt
+          pattern: '^irq([0-7])$'
+        - description: GPIO interrupt
+          pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
+        - description: Bus error interrupt
+          const: bus-err
+        - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
+          const: ec7tie1-0
+        - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
+          const: ec7tie2-0
+        - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
+          const: ec7tiovf-0
+        - description: ECCRAM1 1bit error interrupt
+          const: ec7tie1-1
+        - description: ECCRAM1 2bit error interrupt
+          const: ec7tie2-1
+        - description: ECCRAM1 error overflow interrupt
+          const: ec7tiovf-1
 
   clocks:
     maxItems: 2
-- 
2.43.0

Re: [PATCH v3 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 11:16:44AM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Simplify the bindings by using pattern property for interrupt-names.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change
> v1->v2:
>  * New patch.
> ---
>  .../renesas,rzg2l-irqc.yaml                   | 120 ++++--------------
>  1 file changed, 23 insertions(+), 97 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index 44b6ae5fc802..a0b57d808639 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -48,107 +48,33 @@ properties:
>  
>    interrupts:
>      minItems: 45
> -    items:
> -      - description: NMI interrupt
> -      - description: IRQ0 interrupt

I do not understand how this is related to simplifying interrupt-names.

> -      - description: IRQ1 interrupt
> -      - description: IRQ2 interrupt
> -      - description: IRQ3 interrupt
> -      - description: IRQ4 interrupt
> -      - description: IRQ5 interrupt
> -      - description: IRQ6 interrupt
> -      - description: IRQ7 interrupt
> -      - description: GPIO interrupt, TINT0
> -      - description: GPIO interrupt, TINT1
> -      - description: GPIO interrupt, TINT2
> -      - description: GPIO interrupt, TINT3
> -      - description: GPIO interrupt, TINT4
> -      - description: GPIO interrupt, TINT5
> -      - description: GPIO interrupt, TINT6
> -      - description: GPIO interrupt, TINT7
> -      - description: GPIO interrupt, TINT8
> -      - description: GPIO interrupt, TINT9
> -      - description: GPIO interrupt, TINT10
> -      - description: GPIO interrupt, TINT11
> -      - description: GPIO interrupt, TINT12
> -      - description: GPIO interrupt, TINT13
> -      - description: GPIO interrupt, TINT14
> -      - description: GPIO interrupt, TINT15
> -      - description: GPIO interrupt, TINT16
> -      - description: GPIO interrupt, TINT17
> -      - description: GPIO interrupt, TINT18
> -      - description: GPIO interrupt, TINT19
> -      - description: GPIO interrupt, TINT20
> -      - description: GPIO interrupt, TINT21
> -      - description: GPIO interrupt, TINT22
> -      - description: GPIO interrupt, TINT23
> -      - description: GPIO interrupt, TINT24
> -      - description: GPIO interrupt, TINT25
> -      - description: GPIO interrupt, TINT26
> -      - description: GPIO interrupt, TINT27
> -      - description: GPIO interrupt, TINT28
> -      - description: GPIO interrupt, TINT29
> -      - description: GPIO interrupt, TINT30
> -      - description: GPIO interrupt, TINT31
> -      - description: Bus error interrupt
> -      - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
> -      - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
> -      - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
> -      - description: ECCRAM1 1bit error interrupt
> -      - description: ECCRAM1 2bit error interrupt
> -      - description: ECCRAM1 error overflow interrupt
> +    maxItems: 48
>  
>    interrupt-names:
>      minItems: 45
> +    maxItems: 48
>      items:
> -      - const: nmi
> -      - const: irq0
> -      - const: irq1
> -      - const: irq2
> -      - const: irq3
> -      - const: irq4
> -      - const: irq5
> -      - const: irq6
> -      - const: irq7
> -      - const: tint0
> -      - const: tint1
> -      - const: tint2
> -      - const: tint3
> -      - const: tint4
> -      - const: tint5
> -      - const: tint6
> -      - const: tint7
> -      - const: tint8
> -      - const: tint9
> -      - const: tint10
> -      - const: tint11
> -      - const: tint12
> -      - const: tint13
> -      - const: tint14
> -      - const: tint15
> -      - const: tint16
> -      - const: tint17
> -      - const: tint18
> -      - const: tint19
> -      - const: tint20
> -      - const: tint21
> -      - const: tint22
> -      - const: tint23
> -      - const: tint24
> -      - const: tint25
> -      - const: tint26
> -      - const: tint27
> -      - const: tint28
> -      - const: tint29
> -      - const: tint30
> -      - const: tint31
> -      - const: bus-err
> -      - const: ec7tie1-0
> -      - const: ec7tie2-0
> -      - const: ec7tiovf-0
> -      - const: ec7tie1-1
> -      - const: ec7tie2-1
> -      - const: ec7tiovf-1
> +      oneOf:
> +        - description: NMI interrupt
> +          const: nmi

Your commit msg is completely inaccurate. You are not simplifying, you
are CHANGING by allowing any order.


Best regards,
Krzysztof

RE: [PATCH v3 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the feedback.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 07 February 2026 10:34
> Subject: Re: [PATCH v3 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for
> interrupt-names
> 
> On Fri, Feb 06, 2026 at 11:16:44AM +0000, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Simplify the bindings by using pattern property for interrupt-names.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * No change
> > v1->v2:
> >  * New patch.
> > ---
> >  .../renesas,rzg2l-irqc.yaml                   | 120 ++++--------------
> >  1 file changed, 23 insertions(+), 97 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l
> > -irqc.yaml
> > b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l
> > -irqc.yaml index 44b6ae5fc802..a0b57d808639 100644
> > ---
> > a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l
> > -irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r
> > +++ zg2l-irqc.yaml
> > @@ -48,107 +48,33 @@ properties:
> >
> >    interrupts:
> >      minItems: 45
> > -    items:
> > -      - description: NMI interrupt
> > -      - description: IRQ0 interrupt
> 
> I do not understand how this is related to simplifying interrupt-names.

The list keeps growing, this change simplifies for RZ/G3L SoC that has 61 interrupts.
and it is not something new in bindings see [1]

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/net/snps,dwmac.yaml?h=next-20260205#n125


> 
> > -      - description: IRQ1 interrupt
> > -      - description: IRQ2 interrupt
> > -      - description: IRQ3 interrupt
> > -      - description: IRQ4 interrupt
> > -      - description: IRQ5 interrupt
> > -      - description: IRQ6 interrupt
> > -      - description: IRQ7 interrupt
> > -      - description: GPIO interrupt, TINT0
> > -      - description: GPIO interrupt, TINT1
> > -      - description: GPIO interrupt, TINT2
> > -      - description: GPIO interrupt, TINT3
> > -      - description: GPIO interrupt, TINT4
> > -      - description: GPIO interrupt, TINT5
> > -      - description: GPIO interrupt, TINT6
> > -      - description: GPIO interrupt, TINT7
> > -      - description: GPIO interrupt, TINT8
> > -      - description: GPIO interrupt, TINT9
> > -      - description: GPIO interrupt, TINT10
> > -      - description: GPIO interrupt, TINT11
> > -      - description: GPIO interrupt, TINT12
> > -      - description: GPIO interrupt, TINT13
> > -      - description: GPIO interrupt, TINT14
> > -      - description: GPIO interrupt, TINT15
> > -      - description: GPIO interrupt, TINT16
> > -      - description: GPIO interrupt, TINT17
> > -      - description: GPIO interrupt, TINT18
> > -      - description: GPIO interrupt, TINT19
> > -      - description: GPIO interrupt, TINT20
> > -      - description: GPIO interrupt, TINT21
> > -      - description: GPIO interrupt, TINT22
> > -      - description: GPIO interrupt, TINT23
> > -      - description: GPIO interrupt, TINT24
> > -      - description: GPIO interrupt, TINT25
> > -      - description: GPIO interrupt, TINT26
> > -      - description: GPIO interrupt, TINT27
> > -      - description: GPIO interrupt, TINT28
> > -      - description: GPIO interrupt, TINT29
> > -      - description: GPIO interrupt, TINT30
> > -      - description: GPIO interrupt, TINT31
> > -      - description: Bus error interrupt
> > -      - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
> > -      - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
> > -      - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
> > -      - description: ECCRAM1 1bit error interrupt
> > -      - description: ECCRAM1 2bit error interrupt
> > -      - description: ECCRAM1 error overflow interrupt
> > +    maxItems: 48
> >
> >    interrupt-names:
> >      minItems: 45
> > +    maxItems: 48
> >      items:
> > -      - const: nmi
> > -      - const: irq0
> > -      - const: irq1
> > -      - const: irq2
> > -      - const: irq3
> > -      - const: irq4
> > -      - const: irq5
> > -      - const: irq6
> > -      - const: irq7
> > -      - const: tint0
> > -      - const: tint1
> > -      - const: tint2
> > -      - const: tint3
> > -      - const: tint4
> > -      - const: tint5
> > -      - const: tint6
> > -      - const: tint7
> > -      - const: tint8
> > -      - const: tint9
> > -      - const: tint10
> > -      - const: tint11
> > -      - const: tint12
> > -      - const: tint13
> > -      - const: tint14
> > -      - const: tint15
> > -      - const: tint16
> > -      - const: tint17
> > -      - const: tint18
> > -      - const: tint19
> > -      - const: tint20
> > -      - const: tint21
> > -      - const: tint22
> > -      - const: tint23
> > -      - const: tint24
> > -      - const: tint25
> > -      - const: tint26
> > -      - const: tint27
> > -      - const: tint28
> > -      - const: tint29
> > -      - const: tint30
> > -      - const: tint31
> > -      - const: bus-err
> > -      - const: ec7tie1-0
> > -      - const: ec7tie2-0
> > -      - const: ec7tiovf-0
> > -      - const: ec7tie1-1
> > -      - const: ec7tie2-1
> > -      - const: ec7tiovf-1
> > +      oneOf:
> > +        - description: NMI interrupt
> > +          const: nmi
> 
> Your commit msg is completely inaccurate. You are not simplifying, you are CHANGING by allowing any
> order.

You are correct, apart from keep adding more interrupts in description and items,
it allows to change by any order based on the pattern.

Cheers,
Biju

[PATCH v3 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC
is almost identical to one found on the RZ/G3S SoC with the difference
like it support more External IRQs, GPT Error Interrupts and also has
additional registers for GPT/MTU IRQ selection, shared IRQ selection
between external IRQ and TINT. Hence new generic compatible string
"renesas,r9a08g046-irqc" is added for RZ/G3L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * Dropped items and instead used enum for single compatible values
 * Add minItems for interrupts and interrupt-names properties of 
   the RZ/{G2L,G2UL,Five,V2L} SoCs
 * Replaced maxItems->minItems for interrupts and interrupt-names
   properties of the RZ/G3L SoC.
v1->v2:
 * Simplified the binding using pattern
---
 .../renesas,rzg2l-irqc.yaml                   | 43 ++++++++++++++++---
 1 file changed, 36 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index a0b57d808639..3a221e1800a0 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -30,7 +30,9 @@ properties:
               - renesas,r9a08g045-irqc     # RZ/G3S
           - const: renesas,rzg2l-irqc
 
-      - const: renesas,r9a07g043f-irqc     # RZ/Five
+      - enum:
+          - renesas,r9a07g043f-irqc    # RZ/Five
+          - renesas,r9a08g046-irqc     # RZ/G3L
 
   '#interrupt-cells':
     description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
@@ -48,17 +50,17 @@ properties:
 
   interrupts:
     minItems: 45
-    maxItems: 48
+    maxItems: 61
 
   interrupt-names:
     minItems: 45
-    maxItems: 48
+    maxItems: 61
     items:
       oneOf:
         - description: NMI interrupt
           const: nmi
         - description: External IRQ interrupt
-          pattern: '^irq([0-7])$'
+          pattern: '^irq([0-9]|1[0-5])$'
         - description: GPIO interrupt
           pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
         - description: Bus error interrupt
@@ -75,6 +77,8 @@ properties:
           const: ec7tie2-1
         - description: ECCRAM1 error overflow interrupt
           const: ec7tiovf-1
+        - description: Integrated GPT Error interrupt
+          pattern: '^ovfunf([0-7])$'
 
   clocks:
     maxItems: 2
@@ -106,6 +110,24 @@ required:
 allOf:
   - $ref: /schemas/interrupt-controller.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g043f-irqc
+              - renesas,r9a07g043u-irqc
+              - renesas,r9a07g044-irqc
+              - renesas,r9a07g054-irqc
+    then:
+      properties:
+        interrupts:
+          minItems: 48
+          maxItems: 48
+        interrupt-names:
+          minItems: 48
+          maxItems: 48
+
   - if:
       properties:
         compatible:
@@ -118,12 +140,19 @@ allOf:
           maxItems: 45
         interrupt-names:
           maxItems: 45
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a08g046-irqc
+    then:
       properties:
         interrupts:
-          minItems: 48
+          minItems: 61
         interrupt-names:
-          minItems: 48
+          minItems: 61
 
 unevaluatedProperties: false
 
-- 
2.43.0

Re: [PATCH v3 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 11:16:45AM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC
> is almost identical to one found on the RZ/G3S SoC with the difference
> like it support more External IRQs, GPT Error Interrupts and also has
> additional registers for GPT/MTU IRQ selection, shared IRQ selection
> between external IRQ and TINT. Hence new generic compatible string
> "renesas,r9a08g046-irqc" is added for RZ/G3L SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * Dropped items and instead used enum for single compatible values
>  * Add minItems for interrupts and interrupt-names properties of 
>    the RZ/{G2L,G2UL,Five,V2L} SoCs
>  * Replaced maxItems->minItems for interrupts and interrupt-names
>    properties of the RZ/G3L SoC.
> v1->v2:
>  * Simplified the binding using pattern

Where are lore links to previous dicussions? b4 adds them
automatically.

I do not understand the rationale behind the changes in previous patch
and this makes no sense without previous one, but I feel it was
discussed before. Well, not my task to keep finding them if you decide
not to use standard tools to make review easier :/

Best regards,
Krzysztof

RE: [PATCH v3 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the feedback.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 07 February 2026 10:36
> Subject: Re: [PATCH v3 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
> 
> On Fri, Feb 06, 2026 at 11:16:45AM +0000, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L
> > SoC is almost identical to one found on the RZ/G3S SoC with the
> > difference like it support more External IRQs, GPT Error Interrupts
> > and also has additional registers for GPT/MTU IRQ selection, shared
> > IRQ selection between external IRQ and TINT. Hence new generic
> > compatible string "renesas,r9a08g046-irqc" is added for RZ/G3L SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * Dropped items and instead used enum for single compatible values
> >  * Add minItems for interrupts and interrupt-names properties of
> >    the RZ/{G2L,G2UL,Five,V2L} SoCs
> >  * Replaced maxItems->minItems for interrupts and interrupt-names
> >    properties of the RZ/G3L SoC.
> > v1->v2:
> >  * Simplified the binding using pattern
> 
> Where are lore links to previous dicussions? b4 adds them automatically.

Here is the link [1] and [2]. Next time I will add the lore links. Sorry for not adding.

V2:
[2] https://lore.kernel.org/all/20260205-polar-gifted-lionfish-ef8a8d@quoll/
V1:
[1] https://lore.kernel.org/all/20260204142320.103184-2-biju.das.jz@bp.renesas.com/

Cheers,
Biju

[PATCH v3 3/9] irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct rzg2l_irqc_priv

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The total number of IRQs in RZ/G2L and RZ/G3L SoC are different. The
RZ/G3L has 16 external IRQs where as RZ/G2L has only 8 external IRQ.
Dynamicaly allocate fwspec memory instead of static allocation to support
both SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 drivers/irqchip/irq-renesas-rzg2l.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index e73d426cea6d..20e2b1c4587b 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -79,7 +79,7 @@ struct rzg2l_irqc_reg_cache {
 static struct rzg2l_irqc_priv {
 	void __iomem			*base;
 	const struct irq_chip		*irqchip;
-	struct irq_fwspec		fwspec[IRQC_NUM_IRQ];
+	struct irq_fwspec		*fwspec;
 	raw_spinlock_t			lock;
 	struct rzg2l_irqc_reg_cache	cache;
 } *rzg2l_irqc_data;
@@ -554,6 +554,11 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 	if (IS_ERR(rzg2l_irqc_data->base))
 		return PTR_ERR(rzg2l_irqc_data->base);
 
+	rzg2l_irqc_data->fwspec = devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ,
+					       sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL);
+	if (!rzg2l_irqc_data->fwspec)
+		return -ENOMEM;
+
 	ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
 	if (ret)
 		return dev_err_probe(dev, ret, "cannot parse interrupts: %d\n", ret);
-- 
2.43.0

Re: [PATCH v3 3/9] irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct rzg2l_irqc_priv

[Thomas Gleixner]

On Fri, Feb 06 2026 at 11:16, Biju wrote:

$Subject: ....: Dynamically allocate fwspec array

or such

> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The total number of IRQs in RZ/G2L and RZ/G3L SoC are different. The

s/IRQs/interrupts/

Use proper words and not acronyms. This is not twatter.

> RZ/G3L has 16 external IRQs where as RZ/G2L has only 8 external IRQ.
> Dynamicaly allocate fwspec memory instead of static allocation to support

Dynamically

Thanks,

        tglx

RE: [PATCH v3 3/9] irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct rzg2l_irqc_priv

[Biju Das]

Hi Thomas,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@kernel.org>
> Sent: 06 February 2026 11:42
> Subject: Re: [PATCH v3 3/9] irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct
> rzg2l_irqc_priv
> 
> On Fri, Feb 06 2026 at 11:16, Biju wrote:
> 
> $Subject: ....: Dynamically allocate fwspec array

Ok, will update.

> 
> or such
> 
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > The total number of IRQs in RZ/G2L and RZ/G3L SoC are different. The
> 
> s/IRQs/interrupts/
> 
> Use proper words and not acronyms. This is not twatter.

Agreed.
> 
> > RZ/G3L has 16 external IRQs where as RZ/G2L has only 8 external IRQ.
> > Dynamicaly allocate fwspec memory instead of static allocation to support
> 
> Dynamically

Will fix this in next version.

Cheers,
Biju

[PATCH v3 4/9] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The total number of IRQs in RZ/G2L and RZ/G3L SoC are different.
Introduce struct rzg2l_hw_info to handle the hardware differences and
replace the macro IRQC_NUM_IRQ with num_irq variable in struct
rzg2l_hw_info.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 drivers/irqchip/irq-renesas-rzg2l.c | 46 ++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 20e2b1c4587b..cd9909a85280 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -24,7 +24,6 @@
 #define IRQC_IRQ_COUNT			8
 #define IRQC_TINT_START			(IRQC_IRQ_START + IRQC_IRQ_COUNT)
 #define IRQC_TINT_COUNT			32
-#define IRQC_NUM_IRQ			(IRQC_TINT_START + IRQC_TINT_COUNT)
 
 #define ISCR				0x10
 #define IITSR				0x14
@@ -68,12 +67,21 @@ struct rzg2l_irqc_reg_cache {
 	u32	titsr[2];
 };
 
+/**
+ * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @num_irq:		Total Number of interrupts
+ */
+struct rzg2l_hw_info {
+	u8	num_irq;
+};
+
 /**
  * struct rzg2l_irqc_priv - IRQ controller private data structure
  * @base:	Controller's base address
  * @irqchip:	Pointer to struct irq_chip
  * @fwspec:	IRQ firmware specific data
  * @lock:	Lock to serialize access to hardware registers
+ * @info:	Pointer to struct rzg2l_hw_info
  * @cache:	Registers cache for suspend/resume
  */
 static struct rzg2l_irqc_priv {
@@ -81,6 +89,7 @@ static struct rzg2l_irqc_priv {
 	const struct irq_chip		*irqchip;
 	struct irq_fwspec		*fwspec;
 	raw_spinlock_t			lock;
+	const struct rzg2l_hw_info	*info;
 	struct rzg2l_irqc_reg_cache	cache;
 } *rzg2l_irqc_data;
 
@@ -136,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
 	raw_spin_lock(&priv->lock);
 	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
 		rzg2l_clear_irq_int(priv, hw_irq);
-	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
+	else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
 		rzg2l_clear_tint_int(priv, hw_irq);
 	raw_spin_unlock(&priv->lock);
 	irq_chip_eoi_parent(d);
@@ -182,7 +191,7 @@ static void rzfive_irqc_mask(struct irq_data *d)
 	raw_spin_lock(&priv->lock);
 	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
 		rzfive_irqc_mask_irq_interrupt(priv, hwirq);
-	else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
+	else if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq)
 		rzfive_irqc_mask_tint_interrupt(priv, hwirq);
 	raw_spin_unlock(&priv->lock);
 	irq_chip_mask_parent(d);
@@ -196,7 +205,7 @@ static void rzfive_irqc_unmask(struct irq_data *d)
 	raw_spin_lock(&priv->lock);
 	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
 		rzfive_irqc_unmask_irq_interrupt(priv, hwirq);
-	else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
+	else if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq)
 		rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
 	raw_spin_unlock(&priv->lock);
 	irq_chip_unmask_parent(d);
@@ -207,7 +216,7 @@ static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable)
 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hwirq = irqd_to_hwirq(d);
 
-	if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) {
+	if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq) {
 		u32 offset = hwirq - IRQC_TINT_START;
 		u32 tssr_offset = TSSR_OFFSET(offset);
 		u8 tssr_index = TSSR_INDEX(offset);
@@ -249,9 +258,10 @@ static void rzfive_irqc_irq_enable(struct irq_data *d)
 
 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
 {
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hw_irq = irqd_to_hwirq(d);
 
-	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
+	if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq) {
 		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 		u32 offset = hw_irq - IRQC_TINT_START;
 		u32 tssr_offset = TSSR_OFFSET(offset);
@@ -385,12 +395,13 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
 
 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
 {
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hw_irq = irqd_to_hwirq(d);
 	int ret = -EINVAL;
 
 	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
 		ret = rzg2l_irq_set_type(d, type);
-	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
+	else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
 		ret = rzg2l_tint_set_edge(d, type);
 	if (ret)
 		return ret;
@@ -496,7 +507,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
 			return -EINVAL;
 	}
 
-	if (hwirq > (IRQC_NUM_IRQ - 1))
+	if (hwirq > (priv->info->num_irq - 1))
 		return -EINVAL;
 
 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip,
@@ -520,7 +531,7 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
 	unsigned int i;
 	int ret;
 
-	for (i = 0; i < IRQC_NUM_IRQ; i++) {
+	for (i = 0; i < priv->info->num_irq; i++) {
 		ret = of_irq_parse_one(np, i, &map);
 		if (ret)
 			return ret;
@@ -532,7 +543,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
 }
 
 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_node *parent,
-				   const struct irq_chip *irq_chip)
+				   const struct irq_chip *irq_chip,
+				   const struct rzg2l_hw_info *info)
 {
 	struct irq_domain *irq_domain, *parent_domain;
 	struct device_node *node = pdev->dev.of_node;
@@ -554,7 +566,9 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 	if (IS_ERR(rzg2l_irqc_data->base))
 		return PTR_ERR(rzg2l_irqc_data->base);
 
-	rzg2l_irqc_data->fwspec = devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ,
+	rzg2l_irqc_data->info = info;
+
+	rzg2l_irqc_data->fwspec = devm_kcalloc(&pdev->dev, info->num_irq,
 					       sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL);
 	if (!rzg2l_irqc_data->fwspec)
 		return -ENOMEM;
@@ -579,7 +593,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 
 	raw_spin_lock_init(&rzg2l_irqc_data->lock);
 
-	irq_domain = irq_domain_create_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, dev_fwnode(dev),
+	irq_domain = irq_domain_create_hierarchy(parent_domain, 0, info->num_irq, dev_fwnode(dev),
 						 &rzg2l_irqc_domain_ops, rzg2l_irqc_data);
 	if (!irq_domain) {
 		pm_runtime_put(dev);
@@ -591,14 +605,18 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 	return 0;
 }
 
+static const struct rzg2l_hw_info rzg2l_hw_params = {
+	.num_irq	= IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT,
+};
+
 static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_node *parent)
 {
-	return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip);
+	return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg2l_hw_params);
 }
 
 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_node *parent)
 {
-	return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip);
+	return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip, &rzg2l_hw_params);
 }
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
-- 
2.43.0

Re: [PATCH v3 4/9] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro

[Thomas Gleixner]

On Fri, Feb 06 2026 at 11:16, Biju wrote:
> +/**
> + * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
> + * @num_irq:		Total Number of interrupts
> + */
> +struct rzg2l_hw_info {
> +	u8	num_irq;

Odd data type. Whats wrong with a good old unsigned int?

> +};
> +
>  /**
>   * struct rzg2l_irqc_priv - IRQ controller private data structure
>   * @base:	Controller's base address
>   * @irqchip:	Pointer to struct irq_chip
>   * @fwspec:	IRQ firmware specific data
>   * @lock:	Lock to serialize access to hardware registers
> + * @info:	Pointer to struct rzg2l_hw_info

Why a pointer?

>   * @cache:	Registers cache for suspend/resume
>   */
>  static struct rzg2l_irqc_priv {
> @@ -81,6 +89,7 @@ static struct rzg2l_irqc_priv {
>  	const struct irq_chip		*irqchip;
>  	struct irq_fwspec		*fwspec;
>  	raw_spinlock_t			lock;
> +	const struct rzg2l_hw_info	*info;
>  	struct rzg2l_irqc_reg_cache	cache;
>  } *rzg2l_irqc_data;
>  
> @@ -136,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
>  	raw_spin_lock(&priv->lock);
>  	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
>  		rzg2l_clear_irq_int(priv, hw_irq);
> -	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
> +	else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)

Ah I see. To make this more expensive by accessing yet another cache
line. Simply embed a struct hwinfo into irqc_priv and copy the data into
it at probe time.

 
> -	if (hwirq > (IRQC_NUM_IRQ - 1))
> +	if (hwirq > (priv->info->num_irq - 1))

  hwirq >= priv->info.num_irq

This -1 logic is horrible and error prone.

Thanks,

        tglx

RE: [PATCH v3 4/9] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro

[Biju Das]

Hi Thomas,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@kernel.org>
> Sent: 06 February 2026 11:50
> Subject: Re: [PATCH v3 4/9] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
> 
> On Fri, Feb 06 2026 at 11:16, Biju wrote:
> > +/**
> > + * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
> > + * @num_irq:		Total Number of interrupts
> > + */
> > +struct rzg2l_hw_info {
> > +	u8	num_irq;
> 
> Odd data type. Whats wrong with a good old unsigned int?

Ok will use unsigned int

> 
> > +};
> > +
> >  /**
> >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> >   * @base:	Controller's base address
> >   * @irqchip:	Pointer to struct irq_chip
> >   * @fwspec:	IRQ firmware specific data
> >   * @lock:	Lock to serialize access to hardware registers
> > + * @info:	Pointer to struct rzg2l_hw_info
> 
> Why a pointer?
> 
> >   * @cache:	Registers cache for suspend/resume
> >   */
> >  static struct rzg2l_irqc_priv {
> > @@ -81,6 +89,7 @@ static struct rzg2l_irqc_priv {
> >  	const struct irq_chip		*irqchip;
> >  	struct irq_fwspec		*fwspec;
> >  	raw_spinlock_t			lock;
> > +	const struct rzg2l_hw_info	*info;
> >  	struct rzg2l_irqc_reg_cache	cache;
> >  } *rzg2l_irqc_data;
> >
> > @@ -136,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> >  	raw_spin_lock(&priv->lock);
> >  	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
> >  		rzg2l_clear_irq_int(priv, hw_irq);
> > -	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
> > +	else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
> 
> Ah I see. To make this more expensive by accessing yet another cache line. Simply embed a struct
> hwinfo into irqc_priv and copy the data into it at probe time.

Ok, will simply embed a struct hwinfo into irqc_priv and 
copy the data into it at probe time.

> 
> 
> > -	if (hwirq > (IRQC_NUM_IRQ - 1))
> > +	if (hwirq > (priv->info->num_irq - 1))
> 
>   hwirq >= priv->info.num_irq
> 
> This -1 logic is horrible and error prone.

OK will fix this in next version.

Cheers,
Biju

[PATCH v3 5/9] irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add
tint_start variable in struct rzg2l_hw_info to handle this differences
and drop the macro IRQC_TINT_START.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 drivers/irqchip/irq-renesas-rzg2l.c | 30 +++++++++++++++--------------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index cd9909a85280..e5393306f610 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -22,7 +22,6 @@
 
 #define IRQC_IRQ_START			1
 #define IRQC_IRQ_COUNT			8
-#define IRQC_TINT_START			(IRQC_IRQ_START + IRQC_IRQ_COUNT)
 #define IRQC_TINT_COUNT			32
 
 #define ISCR				0x10
@@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache {
 
 /**
  * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tint_start:		Start of TINT interrupts
  * @num_irq:		Total Number of interrupts
  */
 struct rzg2l_hw_info {
+	u8	tint_start;
 	u8	num_irq;
 };
 
@@ -123,7 +124,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq
 
 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
 {
-	u32 bit = BIT(hwirq - IRQC_TINT_START);
+	u32 bit = BIT(hwirq - priv->info->tint_start);
 	u32 reg;
 
 	reg = readl_relaxed(priv->base + TSCR);
@@ -145,7 +146,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
 	raw_spin_lock(&priv->lock);
 	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
 		rzg2l_clear_irq_int(priv, hw_irq);
-	else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
+	else if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq)
 		rzg2l_clear_tint_int(priv, hw_irq);
 	raw_spin_unlock(&priv->lock);
 	irq_chip_eoi_parent(d);
@@ -170,7 +171,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
 static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
 					    unsigned int hwirq)
 {
-	u32 bit = BIT(hwirq - IRQC_TINT_START);
+	u32 bit = BIT(hwirq - priv->info->tint_start);
 
 	writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK);
 }
@@ -178,7 +179,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
 static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
 					      unsigned int hwirq)
 {
-	u32 bit = BIT(hwirq - IRQC_TINT_START);
+	u32 bit = BIT(hwirq - priv->info->tint_start);
 
 	writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK);
 }
@@ -191,7 +192,7 @@ static void rzfive_irqc_mask(struct irq_data *d)
 	raw_spin_lock(&priv->lock);
 	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
 		rzfive_irqc_mask_irq_interrupt(priv, hwirq);
-	else if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq)
+	else if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq)
 		rzfive_irqc_mask_tint_interrupt(priv, hwirq);
 	raw_spin_unlock(&priv->lock);
 	irq_chip_mask_parent(d);
@@ -205,7 +206,7 @@ static void rzfive_irqc_unmask(struct irq_data *d)
 	raw_spin_lock(&priv->lock);
 	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
 		rzfive_irqc_unmask_irq_interrupt(priv, hwirq);
-	else if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq)
+	else if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq)
 		rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
 	raw_spin_unlock(&priv->lock);
 	irq_chip_unmask_parent(d);
@@ -216,8 +217,8 @@ static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable)
 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hwirq = irqd_to_hwirq(d);
 
-	if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq) {
-		u32 offset = hwirq - IRQC_TINT_START;
+	if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq) {
+		u32 offset = hwirq - priv->info->tint_start;
 		u32 tssr_offset = TSSR_OFFSET(offset);
 		u8 tssr_index = TSSR_INDEX(offset);
 		u32 reg;
@@ -261,9 +262,9 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hw_irq = irqd_to_hwirq(d);
 
-	if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq) {
+	if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq) {
 		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
-		u32 offset = hw_irq - IRQC_TINT_START;
+		u32 offset = hw_irq - priv->info->tint_start;
 		u32 tssr_offset = TSSR_OFFSET(offset);
 		u8 tssr_index = TSSR_INDEX(offset);
 		u32 reg;
@@ -354,7 +355,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
 {
 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hwirq = irqd_to_hwirq(d);
-	u32 titseln = hwirq - IRQC_TINT_START;
+	u32 titseln = hwirq - priv->info->tint_start;
 	u32 tssr_offset = TSSR_OFFSET(titseln);
 	u8 tssr_index = TSSR_INDEX(titseln);
 	u8 index, sense;
@@ -401,7 +402,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
 
 	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
 		ret = rzg2l_irq_set_type(d, type);
-	else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
+	else if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq)
 		ret = rzg2l_tint_set_edge(d, type);
 	if (ret)
 		return ret;
@@ -503,7 +504,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
 		tint = TINT_EXTRACT_GPIOINT(hwirq);
 		hwirq = TINT_EXTRACT_HWIRQ(hwirq);
 
-		if (hwirq < IRQC_TINT_START)
+		if (hwirq < priv->info->tint_start)
 			return -EINVAL;
 	}
 
@@ -606,6 +607,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 }
 
 static const struct rzg2l_hw_info rzg2l_hw_params = {
+	.tint_start	= IRQC_IRQ_START + IRQC_IRQ_COUNT,
 	.num_irq	= IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT,
 };
 
-- 
2.43.0

[PATCH v3 6/9] irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The total number of External IRQs in RZ/G2L and RZ/G3L SoC are different.
The RZ/G3L has 16 external IRQs where as RZ/G2L has only 8 external IRQ.
Add irq_count variable in struct rzg2l_hw_info to handle this differences
and drop the macro IRQC_IRQ_COUNT.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 drivers/irqchip/irq-renesas-rzg2l.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index e5393306f610..0de7db45d4c8 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -21,7 +21,6 @@
 #include <linux/syscore_ops.h>
 
 #define IRQC_IRQ_START			1
-#define IRQC_IRQ_COUNT			8
 #define IRQC_TINT_COUNT			32
 
 #define ISCR				0x10
@@ -68,10 +67,12 @@ struct rzg2l_irqc_reg_cache {
 
 /**
  * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @irq_count:		Number of IRQC interrupts
  * @tint_start:		Start of TINT interrupts
  * @num_irq:		Total Number of interrupts
  */
 struct rzg2l_hw_info {
+	u8	irq_count;
 	u8	tint_start;
 	u8	num_irq;
 };
@@ -144,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
 	unsigned int hw_irq = irqd_to_hwirq(d);
 
 	raw_spin_lock(&priv->lock);
-	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
+	if (hw_irq >= IRQC_IRQ_START && hw_irq <= priv->info->irq_count)
 		rzg2l_clear_irq_int(priv, hw_irq);
 	else if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq)
 		rzg2l_clear_tint_int(priv, hw_irq);
@@ -190,7 +191,7 @@ static void rzfive_irqc_mask(struct irq_data *d)
 	unsigned int hwirq = irqd_to_hwirq(d);
 
 	raw_spin_lock(&priv->lock);
-	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
+	if (hwirq >= IRQC_IRQ_START && hwirq <= priv->info->irq_count)
 		rzfive_irqc_mask_irq_interrupt(priv, hwirq);
 	else if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq)
 		rzfive_irqc_mask_tint_interrupt(priv, hwirq);
@@ -204,7 +205,7 @@ static void rzfive_irqc_unmask(struct irq_data *d)
 	unsigned int hwirq = irqd_to_hwirq(d);
 
 	raw_spin_lock(&priv->lock);
-	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
+	if (hwirq >= IRQC_IRQ_START && hwirq <= priv->info->irq_count)
 		rzfive_irqc_unmask_irq_interrupt(priv, hwirq);
 	else if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq)
 		rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
@@ -400,7 +401,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
 	unsigned int hw_irq = irqd_to_hwirq(d);
 	int ret = -EINVAL;
 
-	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
+	if (hw_irq >= IRQC_IRQ_START && hw_irq <= priv->info->irq_count)
 		ret = rzg2l_irq_set_type(d, type);
 	else if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq)
 		ret = rzg2l_tint_set_edge(d, type);
@@ -500,7 +501,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
 	 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
 	 * in IRQC registers to enable a given gpio pin as interrupt.
 	 */
-	if (hwirq > IRQC_IRQ_COUNT) {
+	if (hwirq > priv->info->irq_count) {
 		tint = TINT_EXTRACT_GPIOINT(hwirq);
 		hwirq = TINT_EXTRACT_HWIRQ(hwirq);
 
@@ -607,8 +608,9 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 }
 
 static const struct rzg2l_hw_info rzg2l_hw_params = {
-	.tint_start	= IRQC_IRQ_START + IRQC_IRQ_COUNT,
-	.num_irq	= IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT,
+	.irq_count	= 8,
+	.tint_start	= IRQC_IRQ_START + 8,
+	.num_irq	= IRQC_IRQ_START + 8 + IRQC_TINT_COUNT,
 };
 
 static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_node *parent)
-- 
2.43.0

[PATCH v3 7/9] irqchip/renesas-rzg2l: Add RZ/G3L support

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The IRQC block on the RZ/G3L SoC is almost identical to the one found on
the RZ/G2L SoC, with the following differences:

 - The number of GPIO interrupts for TINT selection is 113 instead of 123.
 - The pin index and TINT selection index are not in the 1:1 map.
 - The number of External IRQ is 16 instead of 8, out of this 8 IRQs are
   shared with TINT.

Add support for the RZ/G3L driver by filling the rzg2l_hw_info table and
adding LUT for mapping between pin index and TINT selection index.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 drivers/irqchip/irq-renesas-rzg2l.c | 47 +++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 0de7db45d4c8..06c439c98ff5 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -67,14 +67,16 @@ struct rzg2l_irqc_reg_cache {
 
 /**
  * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tssel_lut:		TINT lookup table
  * @irq_count:		Number of IRQC interrupts
  * @tint_start:		Start of TINT interrupts
  * @num_irq:		Total Number of interrupts
  */
 struct rzg2l_hw_info {
-	u8	irq_count;
-	u8	tint_start;
-	u8	num_irq;
+	const u8	*tssel_lut;
+	u8		irq_count;
+	u8		tint_start;
+	u8		num_irq;
 };
 
 /**
@@ -343,6 +345,9 @@ static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg
 	u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
 	u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));
 
+	if (priv->info->tssel_lut)
+		tint = priv->info->tssel_lut[tint];
+
 	/* Clear the relevant byte in reg */
 	reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
 	/* Set TINT and leave TIEN clear */
@@ -607,6 +612,36 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
 	return 0;
 }
 
+/* Mapping based on port index on Table 4.2-1 and GPIOINT on Table 4.6-7 */
+static const u8 rzg3l_tssel_lut[] = {
+	83, 84,					/* P20-P21 */
+	7, 8, 9, 10, 11, 12, 13,		/* P30-P36 */
+	85, 86, 87, 88, 89, 90, 91,		/* P50-P56 */
+	92, 93, 94, 95, 96, 97, 98,		/* P60-P66 */
+	99, 100, 101, 102, 103, 104, 105, 106,	/* P70-P77 */
+	107, 108, 109, 110, 111, 112,		/* P80-P85 */
+	45, 46, 47, 48, 49, 50, 51, 52,		/* PA0-PA7 */
+	53, 54, 55, 56, 57, 58, 59, 60,		/* PB0-PB7 */
+	61, 62,	63,				/* PC0-PC2 */
+	64, 65, 66, 67, 68, 69, 70, 71,		/* PD0-PD7 */
+	72, 73, 74, 75, 76, 77, 78, 79,		/* PE0-PE7 */
+	80, 81, 82,				/* PF0-PF2 */
+	27, 28, 29, 30, 31, 32, 33, 34,		/* PG0-PG7 */
+	35, 36, 37, 38, 39, 40,			/* PH0-PH5 */
+	2, 3, 4, 5, 6,				/* PJ0-PJ4 */
+	41, 42, 43, 44,				/* PK0-PK3 */
+	14, 15, 16, 17, 26,			/* PL0-PL4 */
+	18, 19, 20, 21, 22, 23, 24, 25,		/* PM0-PM7 */
+	0, 1					/* PS0-PS1 */
+};
+
+static const struct rzg2l_hw_info rzg3l_hw_params = {
+	.tssel_lut	= rzg3l_tssel_lut,
+	.irq_count	= 16,
+	.tint_start	= IRQC_IRQ_START + 16,
+	.num_irq	= IRQC_IRQ_START + 16 + IRQC_TINT_COUNT,
+};
+
 static const struct rzg2l_hw_info rzg2l_hw_params = {
 	.irq_count	= 8,
 	.tint_start	= IRQC_IRQ_START + 8,
@@ -618,6 +653,11 @@ static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_node *pa
 	return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg2l_hw_params);
 }
 
+static int rzg3l_irqc_probe(struct platform_device *pdev, struct device_node *parent)
+{
+	return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg3l_hw_params);
+}
+
 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_node *parent)
 {
 	return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip, &rzg2l_hw_params);
@@ -625,6 +665,7 @@ static int rzfive_irqc_probe(struct platform_device *pdev, struct device_node *p
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_probe)
+IRQCHIP_MATCH("renesas,r9a08g046-irqc", rzg3l_irqc_probe)
 IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_probe)
 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
-- 
2.43.0

Re: [PATCH v3 7/9] irqchip/renesas-rzg2l: Add RZ/G3L support

[Thomas Gleixner]

On Fri, Feb 06 2026 at 11:16, Biju wrote:
>  /**
>   * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
> + * @tssel_lut:		TINT lookup table
>   * @irq_count:		Number of IRQC interrupts
>   * @tint_start:		Start of TINT interrupts
>   * @num_irq:		Total Number of interrupts
>   */
>  struct rzg2l_hw_info {
> -	u8	irq_count;
> -	u8	tint_start;
> -	u8	num_irq;
> +	const u8	*tssel_lut;

You can spare that churn by indenting this correctly from the beginning.

> +	u8		irq_count;
> +	u8		tint_start;
> +	u8		num_irq;
>  };

> @@ -343,6 +345,9 @@ static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg
>  	u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
>  	u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));
>  
> +	if (priv->info->tssel_lut)
> +		tint = priv->info->tssel_lut[tint];

I'd rather make it very clear in the code:

	if (priv->info->tssel_lut)
		tint = priv->info->tssel_lut[tint];
        else
        	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);

rather than read first and overwrite somewhere else.
  
> +/* Mapping based on port index on Table 4.2-1 and GPIOINT on Table 4.6-7 */
> +static const u8 rzg3l_tssel_lut[] = {
> +	83, 84,					/* P20-P21 */
> +	7, 8, 9, 10, 11, 12, 13,		/* P30-P36 */
> +	85, 86, 87, 88, 89, 90, 91,		/* P50-P56 */
> +	92, 93, 94, 95, 96, 97, 98,		/* P60-P66 */
> +	99, 100, 101, 102, 103, 104, 105, 106,	/* P70-P77 */

Please format it so it looks like a table:

	 83,  84,				/* P20-P21 */
	  7,   8,   9,  10,  11,  12,  13,	/* P30-P36 */
	 85,  86,  87,  88,  89,  90,  91,	/* P50-P56 */
	 92,  93,  94,  95,  96,  97,  98,	/* P60-P66 */
	 99, 100, 101, 102, 103, 104, 105, 106,	/* P70-P77 */

That's makes it easy to read and to identify the number of entries for a
particular port. The condensed format does not. No?

Thanks,

        tglx

RE: [PATCH v3 7/9] irqchip/renesas-rzg2l: Add RZ/G3L support

[Biju Das]

Hi Thomas,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@kernel.org>
> Sent: 06 February 2026 11:59
> Subject: Re: [PATCH v3 7/9] irqchip/renesas-rzg2l: Add RZ/G3L support
> 
> On Fri, Feb 06 2026 at 11:16, Biju wrote:
> >  /**
> >   * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
> > + * @tssel_lut:		TINT lookup table
> >   * @irq_count:		Number of IRQC interrupts
> >   * @tint_start:		Start of TINT interrupts
> >   * @num_irq:		Total Number of interrupts
> >   */
> >  struct rzg2l_hw_info {
> > -	u8	irq_count;
> > -	u8	tint_start;
> > -	u8	num_irq;
> > +	const u8	*tssel_lut;
> 
> You can spare that churn by indenting this correctly from the beginning.

OK.

> 
> > +	u8		irq_count;
> > +	u8		tint_start;
> > +	u8		num_irq;
> >  };
> 
> > @@ -343,6 +345,9 @@ static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg
> >  	u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
> >  	u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));
> >
> > +	if (priv->info->tssel_lut)
> > +		tint = priv->info->tssel_lut[tint];
> 
> I'd rather make it very clear in the code:
> 
> 	if (priv->info->tssel_lut)
> 		tint = priv->info->tssel_lut[tint];
>         else
>         	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
> 
> rather than read first and overwrite somewhere else.

Agreed.

> 
> > +/* Mapping based on port index on Table 4.2-1 and GPIOINT on Table
> > +4.6-7 */ static const u8 rzg3l_tssel_lut[] = {
> > +	83, 84,					/* P20-P21 */
> > +	7, 8, 9, 10, 11, 12, 13,		/* P30-P36 */
> > +	85, 86, 87, 88, 89, 90, 91,		/* P50-P56 */
> > +	92, 93, 94, 95, 96, 97, 98,		/* P60-P66 */
> > +	99, 100, 101, 102, 103, 104, 105, 106,	/* P70-P77 */
> 
> Please format it so it looks like a table:
> 
> 	 83,  84,				/* P20-P21 */
> 	  7,   8,   9,  10,  11,  12,  13,	/* P30-P36 */
> 	 85,  86,  87,  88,  89,  90,  91,	/* P50-P56 */
> 	 92,  93,  94,  95,  96,  97,  98,	/* P60-P66 */
> 	 99, 100, 101, 102, 103, 104, 105, 106,	/* P70-P77 */
> 
> That's makes it easy to read and to identify the number of entries for a particular port. The
> condensed format does not. No?

OK, will fix this in next version.

Cheers,
Biju

[PATCH v3 8/9] irqchip/renesas-rzg2l: Add shared irq support

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The total number of External IRQs in RZ/G2L and RZ/G3L SoC are different.
The RZ/G3L has 16 external IRQs out of which it shares 8 IRQs with TINT,
where as RZ/G2L has only 8 external IRQ. Add shared_irq variable in
struct rzg2l_hw_info to handle this differences by adding the callback
irq_{request,release}_resources().

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 drivers/irqchip/irq-renesas-rzg2l.c | 94 +++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 06c439c98ff5..59108e1d53ec 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -29,6 +29,8 @@
 #define TITSR(n)			(0x24 + (n) * 4)
 #define TITSR0_MAX_INT			16
 #define TITSEL_WIDTH			0x2
+#define INTTSEL				0x2c
+#define TINTSEL(n)			BIT(n)
 #define TSSR(n)				(0x30 + ((n) * 4))
 #define TIEN				BIT(7)
 #define TSSEL_SHIFT(n)			(8 * (n))
@@ -58,10 +60,12 @@
 /**
  * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
  * @iitsr: IITSR register
+ * @inttsel: INTTSEL register
  * @titsr: TITSR registers
  */
 struct rzg2l_irqc_reg_cache {
 	u32	iitsr;
+	u32	inttsel;
 	u32	titsr[2];
 };
 
@@ -71,12 +75,14 @@ struct rzg2l_irqc_reg_cache {
  * @irq_count:		Number of IRQC interrupts
  * @tint_start:		Start of TINT interrupts
  * @num_irq:		Total Number of interrupts
+ * @shared_irq_cnt:	Number of shared interrupts
  */
 struct rzg2l_hw_info {
 	const u8	*tssel_lut;
 	u8		irq_count;
 	u8		tint_start;
 	u8		num_irq;
+	u8		shared_irq_cnt;
 };
 
 /**
@@ -295,6 +301,87 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
 	irq_chip_enable_parent(d);
 }
 
+static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info *info, unsigned int hw_irq)
+{
+	return ((hw_irq >= (info->tint_start - info->shared_irq_cnt)) &&
+		hw_irq < info->tint_start);
+}
+
+static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info *info, unsigned int hw_irq)
+{
+	return ((hw_irq >= (info->num_irq - info->shared_irq_cnt)) &&
+		hw_irq < info->num_irq);
+}
+
+static int rzg2l_irqc_irq_request_resources(struct irq_data *d)
+{
+	unsigned int hw_irq = irqd_to_hwirq(d);
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
+	const struct rzg2l_hw_info *info = priv->info;
+	u32 offset, tssr_offset;
+	u8 tssr_index, tssel_shift;
+	u32 reg, inttsel_reg;
+	u8 value;
+
+	if (!info->shared_irq_cnt)
+		return 0;
+
+	if (rzg2l_irqc_is_shared_irqc(info, hw_irq)) {
+		offset = hw_irq + IRQC_TINT_COUNT - info->tint_start;
+		tssr_offset = TSSR_OFFSET(offset);
+		tssr_index = TSSR_INDEX(offset);
+		tssel_shift = TSSEL_SHIFT(tssr_offset);
+
+		reg = readl_relaxed(priv->base + TSSR(tssr_index));
+		value = (reg & (TIEN << tssel_shift)) >> tssel_shift;
+		if (value)
+			goto err_conflict;
+
+		raw_spin_lock(&priv->lock);
+		inttsel_reg = readl_relaxed(priv->base + INTTSEL);
+		inttsel_reg |= TINTSEL(offset);
+		writel_relaxed(inttsel_reg, priv->base + INTTSEL);
+		raw_spin_unlock(&priv->lock);
+	} else if (rzg2l_irqc_is_shared_tint(info, hw_irq)) {
+		offset = hw_irq - info->tint_start;
+		tssr_offset = TSSR_OFFSET(offset);
+		tssr_index = TSSR_INDEX(offset);
+
+		inttsel_reg = readl_relaxed(priv->base + INTTSEL);
+		value = (inttsel_reg & TINTSEL(offset)) >> offset;
+		if (value)
+			goto err_conflict;
+	}
+
+	return 0;
+
+err_conflict:
+	pr_err("%s: Shared SPI conflict!\n", __func__);
+	return -EBUSY;
+}
+
+static void rzg2l_irqc_irq_release_resources(struct irq_data *d)
+{
+	unsigned int hw_irq = irqd_to_hwirq(d);
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
+	const struct rzg2l_hw_info *info = priv->info;
+	u32 offset;
+	u8 inttsel_reg;
+
+	if (!priv->info->shared_irq_cnt)
+		return;
+
+	if (rzg2l_irqc_is_shared_irqc(info, hw_irq)) {
+		offset = hw_irq + IRQC_TINT_COUNT - info->tint_start;
+
+		raw_spin_lock(&priv->lock);
+		inttsel_reg = readl_relaxed(priv->base + INTTSEL);
+		inttsel_reg &= ~TINTSEL(offset);
+		writel_relaxed(inttsel_reg, priv->base + INTTSEL);
+		raw_spin_unlock(&priv->lock);
+	}
+}
+
 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
 {
 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
@@ -422,6 +509,8 @@ static int rzg2l_irqc_irq_suspend(void *data)
 	void __iomem *base = rzg2l_irqc_data->base;
 
 	cache->iitsr = readl_relaxed(base + IITSR);
+	if (rzg2l_irqc_data->info->shared_irq_cnt)
+		cache->inttsel = readl_relaxed(base + INTTSEL);
 	for (u8 i = 0; i < 2; i++)
 		cache->titsr[i] = readl_relaxed(base + TITSR(i));
 
@@ -440,6 +529,8 @@ static void rzg2l_irqc_irq_resume(void *data)
 	 */
 	for (u8 i = 0; i < 2; i++)
 		writel_relaxed(cache->titsr[i], base + TITSR(i));
+	if (rzg2l_irqc_data->info->shared_irq_cnt)
+		writel_relaxed(cache->inttsel, base + INTTSEL);
 	writel_relaxed(cache->iitsr, base + IITSR);
 }
 
@@ -459,6 +550,8 @@ static const struct irq_chip rzg2l_irqc_chip = {
 	.irq_unmask		= irq_chip_unmask_parent,
 	.irq_disable		= rzg2l_irqc_irq_disable,
 	.irq_enable		= rzg2l_irqc_irq_enable,
+	.irq_request_resources	= rzg2l_irqc_irq_request_resources,
+	.irq_release_resources	= rzg2l_irqc_irq_release_resources,
 	.irq_get_irqchip_state	= irq_chip_get_parent_state,
 	.irq_set_irqchip_state	= irq_chip_set_parent_state,
 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
@@ -640,6 +733,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params = {
 	.irq_count	= 16,
 	.tint_start	= IRQC_IRQ_START + 16,
 	.num_irq	= IRQC_IRQ_START + 16 + IRQC_TINT_COUNT,
+	.shared_irq_cnt	= 8,
 };
 
 static const struct rzg2l_hw_info rzg2l_hw_params = {
-- 
2.43.0

[PATCH v3 9/9] arm64: dts: renesas: r9a08g046: Add ICU node

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add interrupt control node to RZ/G3L ("R9A08G046") SoC DTSI
and add icu as interrupt-parent of pincontrol.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
This patch depend upon [1]
[1] https://lore.kernel.org/linux-renesas-soc/20260203131048.421708-9-biju.das.jz@bp.renesas.com/T/#u

v2->v3:
 * No change
v1->v2:
 * No change
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 91 ++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index a92a4e07cc10..65dfa145ef59 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -188,6 +188,7 @@ pinctrl: pinctrl@11030000 {
 			gpio-ranges = <&pinctrl 0 0 232>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			interrupt-parent = <&icu>;
 			clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>;
 			power-domains = <&cpg>;
 			resets = <&cpg R9A08G046_GPIO_RSTN>,
@@ -196,6 +197,96 @@ pinctrl: pinctrl@11030000 {
 			reset-names = "rstn", "port", "spare";
 		};
 
+		icu: interrupt-controller@11050000 {
+			compatible = "renesas,r9a08g046-irqc";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0 0x11050000 0 0x10000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "nmi",
+					  "irq0", "irq1", "irq2", "irq3",
+					  "irq4", "irq5", "irq6", "irq7",
+					  "irq8", "irq9", "irq10", "irq11",
+					  "irq12", "irq13", "irq14", "irq15",
+					  "tint0", "tint1", "tint2", "tint3",
+					  "tint4", "tint5", "tint6", "tint7",
+					  "tint8", "tint9", "tint10", "tint11",
+					  "tint12", "tint13", "tint14", "tint15",
+					  "tint16", "tint17", "tint18", "tint19",
+					  "tint20", "tint21", "tint22", "tint23",
+					  "tint24", "tint25", "tint26", "tint27",
+					  "tint28", "tint29", "tint30", "tint31",
+					  "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0",
+					  "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3",
+					  "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7";
+			clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>,
+				 <&cpg CPG_MOD R9A08G046_IA55_PCLK>;
+			clock-names = "clk", "pclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G046_IA55_RESETN>;
+		};
+
 		dmac: dma-controller@11820000 {
 			compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac";
 			reg = <0 0x11820000 0 0x10000>,
-- 
2.43.0

Re: [PATCH v3 0/9] Add RZ/G3L IRQC support

[Thomas Gleixner]

On Fri, Feb 06 2026 at 11:16, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The IRQC block on RZ/G3L SoC is almost identical to one found on the
> RZ/G3S SoC with the difference like it support more External IRQs, GPT
> Error Interrupts and also has additional registers for GPT/MTU IRQ
> selection, shared IRQ selection between external IRQ and TINT.
>
> It has 16 external interrupts of which 8 interrupts are shared with
> TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
> selection is based on a register in the ICU block.

Can you please give people the time to actually look at your patches
before you repost the full series every other day?

RE: [PATCH v3 0/9] Add RZ/G3L IRQC support

[Biju Das]

Hi Thomas Gleixner,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@kernel.org>
> Sent: 06 February 2026 11:38
> Subject: Re: [PATCH v3 0/9] Add RZ/G3L IRQC support
> 
> On Fri, Feb 06 2026 at 11:16, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > The IRQC block on RZ/G3L SoC is almost identical to one found on the
> > RZ/G3S SoC with the difference like it support more External IRQs, GPT
> > Error Interrupts and also has additional registers for GPT/MTU IRQ
> > selection, shared IRQ selection between external IRQ and TINT.
> >
> > It has 16 external interrupts of which 8 interrupts are shared with
> > TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
> > selection is based on a register in the ICU block.
> 
> Can you please give people the time to actually look at your patches before you repost the full series
> every other day?

Sorry for that. Will take care next time.

Thanks,
Biju