Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Thomas Gleixner <tglx@kernel.org>]

On Thu, Jan 29 2026 at 21:24, Prabhakar Lad wrote:
> On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@kernel.org> wrote:
>>
>> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
>> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> >
>> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
>> > that allows software to explicitly assert interrupts toward individual
>> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
>> > interrupt.
>> >
>> > Introduce a debug mechanism to trigger software interrupts on individual
>> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
>> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
>> > explicitly enabled.
>>
>> Can't you reuse/extend the existing mechanism provided by
>> CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
>> instead of implementing yet another ad hoc debugfs magic?
>>
> Can you please point me to a driver which makes use of it? In my case
> the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
> ICU_SWINT.

Care to look what irq_inject_interrupt() does?

It tries first to inject the interrupt via irq_set_irqchip_state(),
which only works when a chip in the hierarchy implements the
chip::irq_set_irqchip_state() callback.

If that fails, it uses the resend mechanism, which utilizes the
chip::irq_retrigger() callback.

I'm sure you know how to grep for drivers which implement one of them :)

Thanks,

        tglx