[PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger

[PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for device tree nodes and devices
- Switch to using dev_err_probe()
- Add software-triggered interrupt support
- Add handling for ICU error IRQs and SWPE trigger
- Document the new debugfs triggers

Cheers,
Prabhakar

Lad Prabhakar (6):
  irqchip/renesas-rzv2h: Use local node pointer
  irqchip/renesas-rzv2h: Use local device pointer in ICU probe
  irqchip/renesas-rzv2h: Switch to using dev_err_probe()
  irqchip/renesas-rzv2h: Add CA55 software interrupt support
  irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger
  Documentation: ABI: Document rzv2h_icu debugfs triggers

 .../ABI/testing/debugfs-renesas-rzv2h-icu     |  24 ++
 drivers/irqchip/irq-renesas-rzv2h.c           | 303 ++++++++++++++++--
 2 files changed, 296 insertions(+), 31 deletions(-)
 create mode 100644 Documentation/ABI/testing/debugfs-renesas-rzv2h-icu

-- 
2.52.0

[PATCH 1/6] irqchip/renesas-rzv2h: Use local node pointer

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Avoid dereferencing pdev->dev.of_node again in rzv2h_icu_probe_common().
Reuse the already available local node pointer when mapping the ICU
register space.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index da2bc43a0e12..20c0cd11ef25 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -570,7 +570,7 @@ static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_no
 
 	platform_set_drvdata(pdev, rzv2h_icu_data);
 
-	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
+	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, node, 0, NULL);
 	if (IS_ERR(rzv2h_icu_data->base))
 		return PTR_ERR(rzv2h_icu_data->base);
 
-- 
2.52.0

[PATCH 2/6] irqchip/renesas-rzv2h: Use local device pointer in ICU probe

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Use a local struct device pointer in rzv2h_icu_probe_common() to avoid
repeated dereferencing of pdev->dev.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 20c0cd11ef25..766b981cf3d8 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -555,57 +555,58 @@ static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_no
 {
 	struct irq_domain *irq_domain, *parent_domain;
 	struct device_node *node = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
 	struct reset_control *resetn;
 	int ret;
 
 	parent_domain = irq_find_host(parent);
 	if (!parent_domain) {
-		dev_err(&pdev->dev, "cannot find parent domain\n");
+		dev_err(dev, "cannot find parent domain\n");
 		return -ENODEV;
 	}
 
-	rzv2h_icu_data = devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);
+	rzv2h_icu_data = devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);
 	if (!rzv2h_icu_data)
 		return -ENOMEM;
 
 	platform_set_drvdata(pdev, rzv2h_icu_data);
 
-	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, node, 0, NULL);
+	rzv2h_icu_data->base = devm_of_iomap(dev, node, 0, NULL);
 	if (IS_ERR(rzv2h_icu_data->base))
 		return PTR_ERR(rzv2h_icu_data->base);
 
 	ret = rzv2h_icu_parse_interrupts(rzv2h_icu_data, node);
 	if (ret) {
-		dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
+		dev_err(dev, "cannot parse interrupts: %d\n", ret);
 		return ret;
 	}
 
-	resetn = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL);
+	resetn = devm_reset_control_get_exclusive_deasserted(dev, NULL);
 	if (IS_ERR(resetn)) {
 		ret = PTR_ERR(resetn);
-		dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret);
+		dev_err(dev, "failed to acquire deasserted reset: %d\n", ret);
 		return ret;
 	}
 
-	ret = devm_pm_runtime_enable(&pdev->dev);
+	ret = devm_pm_runtime_enable(dev);
 	if (ret < 0) {
-		dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret);
+		dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret);
 		return ret;
 	}
 
-	ret = pm_runtime_resume_and_get(&pdev->dev);
+	ret = pm_runtime_resume_and_get(dev);
 	if (ret < 0) {
-		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
+		dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret);
 		return ret;
 	}
 
 	raw_spin_lock_init(&rzv2h_icu_data->lock);
 
 	irq_domain = irq_domain_create_hierarchy(parent_domain, 0, ICU_NUM_IRQ,
-						 dev_fwnode(&pdev->dev), &rzv2h_icu_domain_ops,
+						 dev_fwnode(dev), &rzv2h_icu_domain_ops,
 						 rzv2h_icu_data);
 	if (!irq_domain) {
-		dev_err(&pdev->dev, "failed to add irq domain\n");
+		dev_err(dev, "failed to add irq domain\n");
 		ret = -ENOMEM;
 		goto pm_put;
 	}
@@ -616,12 +617,12 @@ static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_no
 
 	/*
 	 * coccicheck complains about a missing put_device call before returning, but it's a false
-	 * positive. We still need &pdev->dev after successfully returning from this function.
+	 * positive. We still need dev after successfully returning from this function.
 	 */
 	return 0;
 
 pm_put:
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_put(dev);
 
 	return ret;
 }
-- 
2.52.0

[PATCH 3/6] irqchip/renesas-rzv2h: Switch to using dev_err_probe()

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Make use of dev_err_probe() to simplify rzv2h_icu_probe_common().

Keep dev_err() for -ENOMEM paths, as dev_err_probe() does not print for
allocation failures, ensuring they remain visible in logs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 32 ++++++++++-------------------
 1 file changed, 11 insertions(+), 21 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 766b981cf3d8..4aa772ba1a1f 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -560,10 +560,8 @@ static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_no
 	int ret;
 
 	parent_domain = irq_find_host(parent);
-	if (!parent_domain) {
-		dev_err(dev, "cannot find parent domain\n");
-		return -ENODEV;
-	}
+	if (!parent_domain)
+		return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n");
 
 	rzv2h_icu_data = devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);
 	if (!rzv2h_icu_data)
@@ -576,29 +574,21 @@ static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_no
 		return PTR_ERR(rzv2h_icu_data->base);
 
 	ret = rzv2h_icu_parse_interrupts(rzv2h_icu_data, node);
-	if (ret) {
-		dev_err(dev, "cannot parse interrupts: %d\n", ret);
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(dev, ret, "cannot parse interrupts\n");
 
 	resetn = devm_reset_control_get_exclusive_deasserted(dev, NULL);
-	if (IS_ERR(resetn)) {
-		ret = PTR_ERR(resetn);
-		dev_err(dev, "failed to acquire deasserted reset: %d\n", ret);
-		return ret;
-	}
+	if (IS_ERR(resetn))
+		return dev_err_probe(dev, PTR_ERR(resetn),
+				     "failed to acquire deasserted reset\n");
 
 	ret = devm_pm_runtime_enable(dev);
-	if (ret < 0) {
-		dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed\n");
 
 	ret = pm_runtime_resume_and_get(dev);
-	if (ret < 0) {
-		dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed\n");
 
 	raw_spin_lock_init(&rzv2h_icu_data->lock);
 
-- 
2.52.0

[PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
that allows software to explicitly assert interrupts toward individual
CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
interrupt.

Introduce a debug mechanism to trigger software interrupts on individual
Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
explicitly enabled.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 111 ++++++++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 4aa772ba1a1f..7d3ce1d762f0 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -11,16 +11,23 @@
 
 #include <linux/bitfield.h>
 #include <linux/cleanup.h>
+#include <linux/cpu.h>
+#include <linux/debugfs.h>
 #include <linux/err.h>
+#include <linux/fs.h>
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/irq-renesas-rzv2h.h>
 #include <linux/irqdomain.h>
+#include <linux/kconfig.h>
+#include <linux/kstrtox.h>
+#include <linux/moduleparam.h>
 #include <linux/of_platform.h>
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
 #include <linux/spinlock.h>
 #include <linux/syscore_ops.h>
+#include <linux/uaccess.h>
 
 /* DT "interrupts" indexes */
 #define ICU_IRQ_START				1
@@ -40,6 +47,7 @@
 #define ICU_TSCLR				0x24
 #define ICU_TITSR(k)				(0x28 + (k) * 4)
 #define ICU_TSSR(k)				(0x30 + (k) * 4)
+#define ICU_SWINT				0x130
 #define ICU_DMkSELy(k, y)			(0x420 + (k) * 0x20 + (y) * 4)
 #define ICU_DMACKSELk(k)			(0x500 + (k) * 4)
 
@@ -90,6 +98,13 @@
 #define ICU_RZG3E_TSSEL_MAX_VAL			0x8c
 #define ICU_RZV2H_TSSEL_MAX_VAL			0x55
 
+#define ICU_SWINT_NUM				4
+
+static bool enable_icu_debug;
+module_param_named(debug, enable_icu_debug, bool, 0644);
+MODULE_PARM_DESC(debug,
+		 "Enable RZ/V2H ICU debug/diagnostic interrupts (default: false)");
+
 /**
  * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/resume)
  * @nitsr: ICU_NITSR register
@@ -550,6 +565,98 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device
 	return 0;
 }
 
+static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data)
+{
+	u8 cpu = *(u8 *)data;
+
+	pr_debug("SWINT interrupt for CA55 core %u\n", cpu);
+	return IRQ_HANDLED;
+}
+
+static void rzv2h_icu_remove_debugfs(void *file)
+{
+	debugfs_remove(file);
+}
+
+static ssize_t rzv2h_icu_swint_write(struct file *file, const char __user *ubuf,
+				     size_t len, loff_t *ppos)
+{
+	struct rzv2h_icu_priv *priv = file->private_data;
+	unsigned long cpu;
+	char buf[32];
+	int ret;
+
+	len = min(len, sizeof(buf) - 1);
+	if (copy_from_user(buf, ubuf, len))
+		return -EFAULT;
+	buf[len] = '\0';
+
+	ret = kstrtoul(strim(buf), 0, &cpu);
+	if (ret)
+		return ret;
+
+	if (cpu >= ICU_SWINT_NUM || cpu >= nr_cpu_ids)
+		return -EINVAL;
+
+	if (!cpu_online(cpu))
+		return -ENODEV;
+
+	writel(BIT(cpu), priv->base + ICU_SWINT);
+	return len;
+}
+
+static const struct file_operations rzv2h_icu_swint_fops = {
+	.open	= simple_open,
+	.write	= rzv2h_icu_swint_write,
+	.llseek	= noop_llseek,
+};
+
+static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)
+{
+	static const u8 swint_idx[ICU_SWINT_NUM] = { 0, 1, 2, 3 };
+	static const char * const rzv2h_swint_names[] = {
+		"int-ca55-0", "int-ca55-1",
+		"int-ca55-2", "int-ca55-3",
+	};
+	struct device *dev = &pdev->dev;
+	struct dentry *dentry;
+	struct dentry *dir;
+	unsigned int i;
+	int icu_irq;
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_DEBUG_FS) || !enable_icu_debug)
+		return 0;
+
+	dev_info(dev, "RZ/V2H ICU debug interrupts enabled\n");
+
+	for (i = 0; i < ICU_SWINT_NUM; i++) {
+		icu_irq = platform_get_irq_byname(pdev, rzv2h_swint_names[i]);
+		if (icu_irq < 0)
+			return dev_err_probe(dev, icu_irq,
+					     "Failed to get %s IRQ\n", rzv2h_swint_names[i]);
+		ret = devm_request_irq(dev, icu_irq, rzv2h_icu_swint_irq, 0, dev_name(dev),
+				       (void *)&swint_idx[i]);
+		if (ret)
+			return dev_err_probe(dev, ret, "Failed to request SWINT IRQ: %s\n",
+					     rzv2h_swint_names[i]);
+	}
+
+	dir = debugfs_create_dir("rzv2h_icu", NULL);
+	if (IS_ERR(dir))
+		return PTR_ERR(dir);
+
+	ret = devm_add_action_or_reset(dev, rzv2h_icu_remove_debugfs, dir);
+	if (ret)
+		return ret;
+
+	dentry = debugfs_create_file("swint", 0200, dir, rzv2h_icu_data, &rzv2h_icu_swint_fops);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	return devm_add_action_or_reset(dev, rzv2h_icu_remove_debugfs, dentry);
+}
+
 static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_node *parent,
 				  const struct rzv2h_hw_info *hw_info)
 {
@@ -605,6 +712,10 @@ static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_no
 
 	register_syscore(&rzv2h_irqc_syscore);
 
+	ret = rzv2h_icu_setup_debug_irqs(pdev);
+	if (ret)
+		goto pm_put;
+
 	/*
 	 * coccicheck complains about a missing put_device call before returning, but it's a false
 	 * positive. We still need dev after successfully returning from this function.
-- 
2.52.0

[PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
ECC RAM, and CA55/IP error conditions during bring-up and debugging.

When debug support is enabled, register the error IRQ handler and
provide a debugfs write interface to trigger pseudo error generation
via ICU_SWPE for validation.

Account for SoC differences in ECC RAM error register coverage so the
handler only iterates over valid ECC status/clear banks, and route the
RZ/V2N compatible to a probe path with the correct ECC range while
keeping the existing RZ/V2H and RZ/G3E handling.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 141 +++++++++++++++++++++++++++-
 1 file changed, 140 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 7d3ce1d762f0..6dc297220f05 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -21,6 +21,7 @@
 #include <linux/irqdomain.h>
 #include <linux/kconfig.h>
 #include <linux/kstrtox.h>
+#include <linux/minmax.h>
 #include <linux/moduleparam.h>
 #include <linux/of_platform.h>
 #include <linux/pm_runtime.h>
@@ -47,7 +48,15 @@
 #define ICU_TSCLR				0x24
 #define ICU_TITSR(k)				(0x28 + (k) * 4)
 #define ICU_TSSR(k)				(0x30 + (k) * 4)
+#define ICU_BEISR(k)				(0x70  + (k) * 4)
+#define ICU_BECLR(k)				(0x80  + (k) * 4)
+#define ICU_EREISR(k)				(0x90  + (k) * 4)
+#define ICU_ERCLR(k)				(0xE0  + (k) * 4)
 #define ICU_SWINT				0x130
+#define ICU_ERINTA55CTL(k)			(0x338 + (k) * 4)
+#define ICU_ERINTA55CRL(k)			(0x348 + (k) * 4)
+#define ICU_ERINTA55MSK(k)			(0x358 + (k) * 4)
+#define ICU_SWPE				0x370
 #define ICU_DMkSELy(k, y)			(0x420 + (k) * 0x20 + (y) * 4)
 #define ICU_DMACKSELk(k)			(0x500 + (k) * 4)
 
@@ -99,6 +108,9 @@
 #define ICU_RZV2H_TSSEL_MAX_VAL			0x55
 
 #define ICU_SWINT_NUM				4
+#define ICU_SWPE_NUM				16
+#define ICU_NUM_BE				4
+#define ICU_NUM_A55ERR				4
 
 static bool enable_icu_debug;
 module_param_named(debug, enable_icu_debug, bool, 0644);
@@ -123,12 +135,16 @@ struct rzv2h_irqc_reg_cache {
  * @t_offs:		TINT offset
  * @max_tssel:		TSSEL max value
  * @field_width:	TSSR field width
+ * @ecc_start:		Start index of ECC RAM interrupts
+ * @ecc_end:		End index of ECC RAM interrupts
  */
 struct rzv2h_hw_info {
 	const u8	*tssel_lut;
 	u16		t_offs;
 	u8		max_tssel;
 	u8		field_width;
+	u8		ecc_start;
+	u8		ecc_end;
 };
 
 /* DMAC */
@@ -565,6 +581,48 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device
 	return 0;
 }
 
+static irqreturn_t rzv2h_icu_error_irq(int irq, void *data)
+{
+	struct rzv2h_icu_priv *priv = data;
+	const struct rzv2h_hw_info *hw_info = priv->info;
+	void __iomem *base = priv->base;
+	unsigned int k;
+	u32 st;
+
+	/* 1) Bus errors (BEISR0..3) */
+	for (k = 0; k < ICU_NUM_BE; k++) {
+		st = readl(base + ICU_BEISR(k));
+		if (!st)
+			continue;
+
+		writel(st, base + ICU_BECLR(k));
+		pr_debug("rzv2h-icu: BUS error k=%u status=0x%08x\n", k, st);
+	}
+
+	/* 2) ECC RAM errors (EREISR0..X) */
+	for (k = hw_info->ecc_start; k <= hw_info->ecc_end; k++) {
+		st = readl(base + ICU_EREISR(k));
+		if (!st)
+			continue;
+
+		writel(st, base + ICU_ERCLR(k));
+		pr_debug("rzv2h-icu: ECC error k=%u status=0x%08x\n", k, st);
+	}
+
+	/* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */
+	for (k = 0; k < ICU_NUM_A55ERR; k++) {
+		st = readl(base + ICU_ERINTA55CTL(k));
+		if (!st)
+			continue;
+
+		/* there is no relation with status bits so clear all the interrupts */
+		writel(0xffffffff, base + ICU_ERINTA55CRL(k));
+		pr_debug("rzv2h-icu: IP/CA55 error k=%u status=0x%08x\n", k, st);
+	}
+
+	return IRQ_HANDLED;
+}
+
 static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data)
 {
 	u8 cpu = *(u8 *)data;
@@ -611,13 +669,47 @@ static const struct file_operations rzv2h_icu_swint_fops = {
 	.llseek	= noop_llseek,
 };
 
+static ssize_t rzv2h_icu_swpe_write(struct file *file,
+				    const char __user *ubuf,
+				    size_t len, loff_t *ppos)
+{
+	struct rzv2h_icu_priv *priv = file->private_data;
+	unsigned long swpe;
+	char buf[32];
+	int ret;
+
+	len = min(len, sizeof(buf) - 1);
+	if (copy_from_user(buf, ubuf, len))
+		return -EFAULT;
+	buf[len] = '\0';
+
+	ret = kstrtoul(strim(buf), 0, &swpe);
+	if (ret)
+		return ret;
+
+	if (swpe >= ICU_SWPE_NUM)
+		return -EINVAL;
+
+	writel(BIT(swpe), priv->base + ICU_SWPE);
+	return len;
+}
+
+static const struct file_operations rzv2h_icu_swpe_fops = {
+	.open	= simple_open,
+	.write	= rzv2h_icu_swpe_write,
+	.llseek	= noop_llseek,
+};
+
 static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)
 {
+	const struct rzv2h_hw_info *hw_info = rzv2h_icu_data->info;
 	static const u8 swint_idx[ICU_SWINT_NUM] = { 0, 1, 2, 3 };
 	static const char * const rzv2h_swint_names[] = {
 		"int-ca55-0", "int-ca55-1",
 		"int-ca55-2", "int-ca55-3",
 	};
+	static const char *icu_err = "icu-error-ca55";
+	void __iomem *base = rzv2h_icu_data->base;
 	struct device *dev = &pdev->dev;
 	struct dentry *dentry;
 	struct dentry *dir;
@@ -654,6 +746,36 @@ static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)
 	if (IS_ERR(dentry))
 		return PTR_ERR(dentry);
 
+	ret = devm_add_action_or_reset(dev, rzv2h_icu_remove_debugfs, dentry);
+	if (ret)
+		return ret;
+
+	icu_irq = platform_get_irq_byname(pdev, icu_err);
+	if (icu_irq < 0)
+		return dev_err_probe(dev, icu_irq, "Failed to get %s IRQ\n", icu_err);
+
+	/* Unmask and clear all IP/CA55 error interrupts */
+	for (i = 0; i < ICU_NUM_A55ERR; i++) {
+		writel(0xffffff, base + ICU_ERINTA55CRL(i));
+		writel(0x0, base + ICU_ERINTA55MSK(i));
+	}
+
+	/* Clear all Bus errors */
+	for (i = 0; i < ICU_NUM_BE; i++)
+		writel(0xffffffff, base + ICU_BECLR(i));
+
+	/* Clear all ECCRAM errors */
+	for (i = hw_info->ecc_start; i <= hw_info->ecc_end; i++)
+		writel(0xffffffff, base + ICU_ERCLR(i));
+
+	ret = devm_request_irq(dev, icu_irq, rzv2h_icu_error_irq, 0, dev_name(dev), rzv2h_icu_data);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", icu_err);
+
+	dentry = debugfs_create_file("swpe", 0200, dir, rzv2h_icu_data, &rzv2h_icu_swpe_fops);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
 	return devm_add_action_or_reset(dev, rzv2h_icu_remove_debugfs, dentry);
 }
 
@@ -759,12 +881,24 @@ static const struct rzv2h_hw_info rzg3e_hw_params = {
 	.t_offs		= ICU_RZG3E_TINT_OFFSET,
 	.max_tssel	= ICU_RZG3E_TSSEL_MAX_VAL,
 	.field_width	= 16,
+	.ecc_start	= 1,
+	.ecc_end	= 4,
+};
+
+static const struct rzv2h_hw_info rzv2n_hw_params = {
+	.t_offs		= 0,
+	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
+	.field_width	= 8,
+	.ecc_start	= 0,
+	.ecc_end	= 2,
 };
 
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs		= 0,
 	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
 	.field_width	= 8,
+	.ecc_start	= 0,
+	.ecc_end	= 11,
 };
 
 static int rzg3e_icu_probe(struct platform_device *pdev, struct device_node *parent)
@@ -772,6 +906,11 @@ static int rzg3e_icu_probe(struct platform_device *pdev, struct device_node *par
 	return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params);
 }
 
+static int rzv2n_icu_probe(struct platform_device *pdev, struct device_node *parent)
+{
+	return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params);
+}
+
 static int rzv2h_icu_probe(struct platform_device *pdev, struct device_node *parent)
 {
 	return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params);
@@ -779,7 +918,7 @@ static int rzv2h_icu_probe(struct platform_device *pdev, struct device_node *par
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
 IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe)
-IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2h_icu_probe)
+IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
-- 
2.52.0

[PATCH 6/6] Documentation: ABI: Document rzv2h_icu debugfs triggers

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the debugfs interface exported by the Renesas RZ/V2H ICU
driver to aid bring-up and debugging.

Describe the write-only swint and swpe files used to trigger software
and pseudo error interrupts.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../ABI/testing/debugfs-renesas-rzv2h-icu     | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/ABI/testing/debugfs-renesas-rzv2h-icu

diff --git a/Documentation/ABI/testing/debugfs-renesas-rzv2h-icu b/Documentation/ABI/testing/debugfs-renesas-rzv2h-icu
new file mode 100644
index 000000000000..8e97f35c3fea
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-renesas-rzv2h-icu
@@ -0,0 +1,24 @@
+What:		/sys/kernel/debug/rzv2h_icu/swint
+Date:		Jan 2026
+KernelVersion:	6.20
+Contact:	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+Description:	Write-only debugfs file to trigger ICU software interrupts
+		(ICU_SWINT) targeting CA55 cores.
+		Writing an integer CPU index 'N' causes the driver to write
+		BIT(N) to the ICU_SWINT register, which triggers the hardware
+		software interrupt routed to CA55 core N via the GIC.
+		Valid values:
+		  0..3  - trigger SWINT for CA55 core0..core3
+		The driver validates that the requested CPU is online before
+		triggering the interrupt. Writes for offline CPUs fail.
+
+What:		/sys/kernel/debug/rzv2h_icu/swpe
+Date:		Jan 2026
+KernelVersion:	6.20
+Contact:	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+Description:	Write-only debugfs file to trigger ICU software peripheral
+		events (ICU_SWPE).
+		Writing an integer index 'N' causes the driver to write BIT(N)
+		to the ICU_SWPE register.
+		Valid values:
+		  0..15 - assert SWPE bit 0..15
-- 
2.52.0

RE: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 21 January 2026 15:02
> Subject: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Handle the RZ/V2H ICU error interrupt to help diagnose latched bus, ECC RAM, and CA55/IP error
> conditions during bring-up and debugging.


Just a question,
If the irq handler is meant for debugging/bring-up, can this irq handler activated only for debug session
instead of unconditionally enabling it?

Cheers,
Biju
> 
> When debug support is enabled, register the error IRQ handler and provide a debugfs write interface to
> trigger pseudo error generation via ICU_SWPE for validation.
> 
> Account for SoC differences in ECC RAM error register coverage so the handler only iterates over valid
> ECC status/clear banks, and route the RZ/V2N compatible to a probe path with the correct ECC range
> while keeping the existing RZ/V2H and RZ/G3E handling.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 141 +++++++++++++++++++++++++++-
>  1 file changed, 140 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index 7d3ce1d762f0..6dc297220f05 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -21,6 +21,7 @@
>  #include <linux/irqdomain.h>
>  #include <linux/kconfig.h>
>  #include <linux/kstrtox.h>
> +#include <linux/minmax.h>
>  #include <linux/moduleparam.h>
>  #include <linux/of_platform.h>
>  #include <linux/pm_runtime.h>
> @@ -47,7 +48,15 @@
>  #define ICU_TSCLR				0x24
>  #define ICU_TITSR(k)				(0x28 + (k) * 4)
>  #define ICU_TSSR(k)				(0x30 + (k) * 4)
> +#define ICU_BEISR(k)				(0x70  + (k) * 4)
> +#define ICU_BECLR(k)				(0x80  + (k) * 4)
> +#define ICU_EREISR(k)				(0x90  + (k) * 4)
> +#define ICU_ERCLR(k)				(0xE0  + (k) * 4)
>  #define ICU_SWINT				0x130
> +#define ICU_ERINTA55CTL(k)			(0x338 + (k) * 4)
> +#define ICU_ERINTA55CRL(k)			(0x348 + (k) * 4)
> +#define ICU_ERINTA55MSK(k)			(0x358 + (k) * 4)
> +#define ICU_SWPE				0x370
>  #define ICU_DMkSELy(k, y)			(0x420 + (k) * 0x20 + (y) * 4)
>  #define ICU_DMACKSELk(k)			(0x500 + (k) * 4)
> 
> @@ -99,6 +108,9 @@
>  #define ICU_RZV2H_TSSEL_MAX_VAL			0x55
> 
>  #define ICU_SWINT_NUM				4
> +#define ICU_SWPE_NUM				16
> +#define ICU_NUM_BE				4
> +#define ICU_NUM_A55ERR				4
> 
>  static bool enable_icu_debug;
>  module_param_named(debug, enable_icu_debug, bool, 0644); @@ -123,12 +135,16 @@ struct
> rzv2h_irqc_reg_cache {
>   * @t_offs:		TINT offset
>   * @max_tssel:		TSSEL max value
>   * @field_width:	TSSR field width
> + * @ecc_start:		Start index of ECC RAM interrupts
> + * @ecc_end:		End index of ECC RAM interrupts
>   */
>  struct rzv2h_hw_info {
>  	const u8	*tssel_lut;
>  	u16		t_offs;
>  	u8		max_tssel;
>  	u8		field_width;
> +	u8		ecc_start;
> +	u8		ecc_end;
>  };
> 
>  /* DMAC */
> @@ -565,6 +581,48 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device
>  	return 0;
>  }
> 
> +static irqreturn_t rzv2h_icu_error_irq(int irq, void *data) {
> +	struct rzv2h_icu_priv *priv = data;
> +	const struct rzv2h_hw_info *hw_info = priv->info;
> +	void __iomem *base = priv->base;
> +	unsigned int k;
> +	u32 st;
> +
> +	/* 1) Bus errors (BEISR0..3) */
> +	for (k = 0; k < ICU_NUM_BE; k++) {
> +		st = readl(base + ICU_BEISR(k));
> +		if (!st)
> +			continue;
> +
> +		writel(st, base + ICU_BECLR(k));
> +		pr_debug("rzv2h-icu: BUS error k=%u status=0x%08x\n", k, st);
> +	}
> +
> +	/* 2) ECC RAM errors (EREISR0..X) */
> +	for (k = hw_info->ecc_start; k <= hw_info->ecc_end; k++) {
> +		st = readl(base + ICU_EREISR(k));
> +		if (!st)
> +			continue;
> +
> +		writel(st, base + ICU_ERCLR(k));
> +		pr_debug("rzv2h-icu: ECC error k=%u status=0x%08x\n", k, st);
> +	}
> +
> +	/* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */
> +	for (k = 0; k < ICU_NUM_A55ERR; k++) {
> +		st = readl(base + ICU_ERINTA55CTL(k));
> +		if (!st)
> +			continue;
> +
> +		/* there is no relation with status bits so clear all the interrupts */
> +		writel(0xffffffff, base + ICU_ERINTA55CRL(k));
> +		pr_debug("rzv2h-icu: IP/CA55 error k=%u status=0x%08x\n", k, st);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
>  static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data)  {
>  	u8 cpu = *(u8 *)data;
> @@ -611,13 +669,47 @@ static const struct file_operations rzv2h_icu_swint_fops = {
>  	.llseek	= noop_llseek,
>  };
> 
> +static ssize_t rzv2h_icu_swpe_write(struct file *file,
> +				    const char __user *ubuf,
> +				    size_t len, loff_t *ppos)
> +{
> +	struct rzv2h_icu_priv *priv = file->private_data;
> +	unsigned long swpe;
> +	char buf[32];
> +	int ret;
> +
> +	len = min(len, sizeof(buf) - 1);
> +	if (copy_from_user(buf, ubuf, len))
> +		return -EFAULT;
> +	buf[len] = '\0';
> +
> +	ret = kstrtoul(strim(buf), 0, &swpe);
> +	if (ret)
> +		return ret;
> +
> +	if (swpe >= ICU_SWPE_NUM)
> +		return -EINVAL;
> +
> +	writel(BIT(swpe), priv->base + ICU_SWPE);
> +	return len;
> +}
> +
> +static const struct file_operations rzv2h_icu_swpe_fops = {
> +	.open	= simple_open,
> +	.write	= rzv2h_icu_swpe_write,
> +	.llseek	= noop_llseek,
> +};
> +
>  static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)  {
> +	const struct rzv2h_hw_info *hw_info = rzv2h_icu_data->info;
>  	static const u8 swint_idx[ICU_SWINT_NUM] = { 0, 1, 2, 3 };
>  	static const char * const rzv2h_swint_names[] = {
>  		"int-ca55-0", "int-ca55-1",
>  		"int-ca55-2", "int-ca55-3",
>  	};
> +	static const char *icu_err = "icu-error-ca55";
> +	void __iomem *base = rzv2h_icu_data->base;
>  	struct device *dev = &pdev->dev;
>  	struct dentry *dentry;
>  	struct dentry *dir;
> @@ -654,6 +746,36 @@ static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)
>  	if (IS_ERR(dentry))
>  		return PTR_ERR(dentry);
> 
> +	ret = devm_add_action_or_reset(dev, rzv2h_icu_remove_debugfs, dentry);
> +	if (ret)
> +		return ret;
> +
> +	icu_irq = platform_get_irq_byname(pdev, icu_err);
> +	if (icu_irq < 0)
> +		return dev_err_probe(dev, icu_irq, "Failed to get %s IRQ\n",
> +icu_err);
> +
> +	/* Unmask and clear all IP/CA55 error interrupts */
> +	for (i = 0; i < ICU_NUM_A55ERR; i++) {
> +		writel(0xffffff, base + ICU_ERINTA55CRL(i));
> +		writel(0x0, base + ICU_ERINTA55MSK(i));
> +	}
> +
> +	/* Clear all Bus errors */
> +	for (i = 0; i < ICU_NUM_BE; i++)
> +		writel(0xffffffff, base + ICU_BECLR(i));
> +
> +	/* Clear all ECCRAM errors */
> +	for (i = hw_info->ecc_start; i <= hw_info->ecc_end; i++)
> +		writel(0xffffffff, base + ICU_ERCLR(i));
> +
> +	ret = devm_request_irq(dev, icu_irq, rzv2h_icu_error_irq, 0, dev_name(dev), rzv2h_icu_data);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to request %s IRQ\n",
> +icu_err);
> +
> +	dentry = debugfs_create_file("swpe", 0200, dir, rzv2h_icu_data, &rzv2h_icu_swpe_fops);
> +	if (IS_ERR(dentry))
> +		return PTR_ERR(dentry);
> +
>  	return devm_add_action_or_reset(dev, rzv2h_icu_remove_debugfs, dentry);  }
> 
> @@ -759,12 +881,24 @@ static const struct rzv2h_hw_info rzg3e_hw_params = {
>  	.t_offs		= ICU_RZG3E_TINT_OFFSET,
>  	.max_tssel	= ICU_RZG3E_TSSEL_MAX_VAL,
>  	.field_width	= 16,
> +	.ecc_start	= 1,
> +	.ecc_end	= 4,
> +};
> +
> +static const struct rzv2h_hw_info rzv2n_hw_params = {
> +	.t_offs		= 0,
> +	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
> +	.field_width	= 8,
> +	.ecc_start	= 0,
> +	.ecc_end	= 2,
>  };
> 
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs		= 0,
>  	.max_tssel	= ICU_RZV2H_TSSEL_MAX_VAL,
>  	.field_width	= 8,
> +	.ecc_start	= 0,
> +	.ecc_end	= 11,
>  };
> 
>  static int rzg3e_icu_probe(struct platform_device *pdev, struct device_node *parent) @@ -772,6
> +906,11 @@ static int rzg3e_icu_probe(struct platform_device *pdev, struct device_node *par
>  	return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params);  }
> 
> +static int rzv2n_icu_probe(struct platform_device *pdev, struct
> +device_node *parent) {
> +	return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params); }
> +
>  static int rzv2h_icu_probe(struct platform_device *pdev, struct device_node *parent)  {
>  	return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params); @@ -779,7 +918,7 @@ static int
> rzv2h_icu_probe(struct platform_device *pdev, struct device_node *par
> 
>  IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
>  IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe) -IRQCHIP_MATCH("renesas,r9a09g056-icu",
> rzv2h_icu_probe)
> +IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe)
>  IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe)
>  IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
>  MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
> --
> 2.52.0

Re: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger

[Lad, Prabhakar]

Hi Biju,

On Thu, Jan 22, 2026 at 8:20 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 21 January 2026 15:02
> > Subject: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Handle the RZ/V2H ICU error interrupt to help diagnose latched bus, ECC RAM, and CA55/IP error
> > conditions during bring-up and debugging.
>
>
> Just a question,
> If the irq handler is meant for debugging/bring-up, can this irq handler activated only for debug session
> instead of unconditionally enabling it?
>
The IRQ handler is registered only when `irq_renesas_rzv2h.debug=1` is
present in the bootargs.

Cheers,
Prabhakar

RE: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 22 January 2026 09:19
> Subject: Re: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger
> 
> Hi Biju,
> 
> On Thu, Jan 22, 2026 at 8:20 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: 21 January 2026 15:02
> > > Subject: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and
> > > add SWPE trigger
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
> > > ECC RAM, and CA55/IP error conditions during bring-up and debugging.
> >
> >
> > Just a question,
> > If the irq handler is meant for debugging/bring-up, can this irq
> > handler activated only for debug session instead of unconditionally enabling it?
> >
> The IRQ handler is registered only when `irq_renesas_rzv2h.debug=1` is present in the bootargs.

Thanks for clarification.

Cheers,
Biju

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, 21 Jan 2026 at 16:01, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> that allows software to explicitly assert interrupts toward individual
> CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> interrupt.
>
> Introduce a debug mechanism to trigger software interrupts on individual
> Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> explicitly enabled.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -11,16 +11,23 @@
>
>  #include <linux/bitfield.h>
>  #include <linux/cleanup.h>
> +#include <linux/cpu.h>
> +#include <linux/debugfs.h>
>  #include <linux/err.h>
> +#include <linux/fs.h>
>  #include <linux/io.h>
>  #include <linux/irqchip.h>
>  #include <linux/irqchip/irq-renesas-rzv2h.h>
>  #include <linux/irqdomain.h>
> +#include <linux/kconfig.h>
> +#include <linux/kstrtox.h>
> +#include <linux/moduleparam.h>
>  #include <linux/of_platform.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/reset.h>
>  #include <linux/spinlock.h>
>  #include <linux/syscore_ops.h>
> +#include <linux/uaccess.h>
>

[...]

> +static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)
> +{
> +       static const u8 swint_idx[ICU_SWINT_NUM] = { 0, 1, 2, 3 };
> +       static const char * const rzv2h_swint_names[] = {
> +               "int-ca55-0", "int-ca55-1",
> +               "int-ca55-2", "int-ca55-3",
> +       };
> +       struct device *dev = &pdev->dev;
> +       struct dentry *dentry;
> +       struct dentry *dir;
> +       unsigned int i;
> +       int icu_irq;
> +       int ret;
> +
> +       if (!IS_ENABLED(CONFIG_DEBUG_FS) || !enable_icu_debug)
> +               return 0;
> +
> +       dev_info(dev, "RZ/V2H ICU debug interrupts enabled\n");
> +
> +       for (i = 0; i < ICU_SWINT_NUM; i++) {
> +               icu_irq = platform_get_irq_byname(pdev, rzv2h_swint_names[i]);
> +               if (icu_irq < 0)
> +                       return dev_err_probe(dev, icu_irq,
> +                                            "Failed to get %s IRQ\n", rzv2h_swint_names[i]);
> +               ret = devm_request_irq(dev, icu_irq, rzv2h_icu_swint_irq, 0, dev_name(dev),
> +                                      (void *)&swint_idx[i]);

drivers/irqchip/irq-renesas-rzv2h.c:730:23: error: implicit
declaration of function ‘devm_request_irq’; did you mean
‘can_request_irq’? [-Werror=implicit-function-declaration]

How does this build for you, without including <linux/interrupt.h>?

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Fri, Jan 23, 2026 at 10:45 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 21 Jan 2026 at 16:01, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> > that allows software to explicitly assert interrupts toward individual
> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> > interrupt.
> >
> > Introduce a debug mechanism to trigger software interrupts on individual
> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> > explicitly enabled.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > @@ -11,16 +11,23 @@
> >
> >  #include <linux/bitfield.h>
> >  #include <linux/cleanup.h>
> > +#include <linux/cpu.h>
> > +#include <linux/debugfs.h>
> >  #include <linux/err.h>
> > +#include <linux/fs.h>
> >  #include <linux/io.h>
> >  #include <linux/irqchip.h>
> >  #include <linux/irqchip/irq-renesas-rzv2h.h>
> >  #include <linux/irqdomain.h>
> > +#include <linux/kconfig.h>
> > +#include <linux/kstrtox.h>
> > +#include <linux/moduleparam.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/reset.h>
> >  #include <linux/spinlock.h>
> >  #include <linux/syscore_ops.h>
> > +#include <linux/uaccess.h>
> >
>
> [...]
>
> > +static int rzv2h_icu_setup_debug_irqs(struct platform_device *pdev)
> > +{
> > +       static const u8 swint_idx[ICU_SWINT_NUM] = { 0, 1, 2, 3 };
> > +       static const char * const rzv2h_swint_names[] = {
> > +               "int-ca55-0", "int-ca55-1",
> > +               "int-ca55-2", "int-ca55-3",
> > +       };
> > +       struct device *dev = &pdev->dev;
> > +       struct dentry *dentry;
> > +       struct dentry *dir;
> > +       unsigned int i;
> > +       int icu_irq;
> > +       int ret;
> > +
> > +       if (!IS_ENABLED(CONFIG_DEBUG_FS) || !enable_icu_debug)
> > +               return 0;
> > +
> > +       dev_info(dev, "RZ/V2H ICU debug interrupts enabled\n");
> > +
> > +       for (i = 0; i < ICU_SWINT_NUM; i++) {
> > +               icu_irq = platform_get_irq_byname(pdev, rzv2h_swint_names[i]);
> > +               if (icu_irq < 0)
> > +                       return dev_err_probe(dev, icu_irq,
> > +                                            "Failed to get %s IRQ\n", rzv2h_swint_names[i]);
> > +               ret = devm_request_irq(dev, icu_irq, rzv2h_icu_swint_irq, 0, dev_name(dev),
> > +                                      (void *)&swint_idx[i]);
>
> drivers/irqchip/irq-renesas-rzv2h.c:730:23: error: implicit
> declaration of function ‘devm_request_irq’; did you mean
> ‘can_request_irq’? [-Werror=implicit-function-declaration]
>
> How does this build for you, without including <linux/interrupt.h>?
>
While posting the patches, I had rebased them on next-20260119 (and
used defconfig), but I didn't see any build issues. Below is the
snippet from irq-renesas-rzv2h.i:

struct ns_common;
int open_related_ns(struct ns_common *ns, struct ns_common
*(*get_ns)(struct ns_common *ns));

static inline __attribute__((__gnu_inline__))
__attribute__((__unused__))
__attribute__((__no_instrument_function__)) struct pid_namespace
*proc_pid_ns(struct super_block *sb)
{
return proc_sb_info(sb)->pid_ns;
}

bool proc_ns_file(const struct file *file);
# 20 "./include/linux/efi.h" 2
# 1 "./include/linux/rtc.h" 1
# 17 "./include/linux/rtc.h"
# 1 "./include/linux/interrupt.h" 1
# 9 "./include/linux/interrupt.h"
# 1 "./include/linux/irqreturn.h" 1
# 11 "./include/linux/irqreturn.h"

enum irqreturn {
IRQ_NONE = (0 << 0),
IRQ_HANDLED = (1 << 0),
IRQ_WAKE_THREAD = (1 << 1),
};

typedef enum irqreturn irqreturn_t;
# 10 "./include/linux/interrupt.h" 2
# 1 "./include/linux/hardirq.h" 1


Tracing through the above interrupt.h was included in below :
-------------------------------------------------------------------------------
drivers/irqchip/irq-renesas-rzv2h.c - (line 19)
#include <linux/irqchip.h>
#include <linux/acpi.h>
#include <acpi/acpi_io.h>
#include <asm/acpi.h>
#include <linux/efi.h>
#include <linux/rtc.h>
#include <linux/interrupt.h>


Now that you mentioned there was a build issue, I tried with
renesas_defconfig and I do get the build issue which you pointed out.
I'll respin a v2 with #include <linux/interrupt.h> included
explicitly.

Cheers,
Prabhakar

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Thomas Gleixner]

On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> that allows software to explicitly assert interrupts toward individual
> CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> interrupt.
>
> Introduce a debug mechanism to trigger software interrupts on individual
> Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> explicitly enabled.

Can't you reuse/extend the existing mechanism provided by
CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
instead of implementing yet another ad hoc debugfs magic?

Thanks,

        tglx
       

Re: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger

[Thomas Gleixner]

On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
> ECC RAM, and CA55/IP error conditions during bring-up and debugging.

Why is that only relevant to bring-up and debugging? Those errors
can't happen in production, right?

Thanks,

        tglx

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Lad, Prabhakar]

Hi Thomas,

Thank you for the feedback.

On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@kernel.org> wrote:
>
> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> > that allows software to explicitly assert interrupts toward individual
> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> > interrupt.
> >
> > Introduce a debug mechanism to trigger software interrupts on individual
> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> > explicitly enabled.
>
> Can't you reuse/extend the existing mechanism provided by
> CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
> instead of implementing yet another ad hoc debugfs magic?
>
Can you please point me to a driver which makes use of it? In my case
the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
ICU_SWINT.

Cheers,
Prabhakar

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Thomas Gleixner]

On Thu, Jan 29 2026 at 21:24, Prabhakar Lad wrote:
> On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@kernel.org> wrote:
>>
>> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
>> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> >
>> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
>> > that allows software to explicitly assert interrupts toward individual
>> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
>> > interrupt.
>> >
>> > Introduce a debug mechanism to trigger software interrupts on individual
>> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
>> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
>> > explicitly enabled.
>>
>> Can't you reuse/extend the existing mechanism provided by
>> CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
>> instead of implementing yet another ad hoc debugfs magic?
>>
> Can you please point me to a driver which makes use of it? In my case
> the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
> ICU_SWINT.

Care to look what irq_inject_interrupt() does?

It tries first to inject the interrupt via irq_set_irqchip_state(),
which only works when a chip in the hierarchy implements the
chip::irq_set_irqchip_state() callback.

If that fails, it uses the resend mechanism, which utilizes the
chip::irq_retrigger() callback.

I'm sure you know how to grep for drivers which implement one of them :)

Thanks,

        tglx

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Lad, Prabhakar]

Hi Thomas,

On Thu, Jan 29, 2026 at 9:59 PM Thomas Gleixner <tglx@kernel.org> wrote:
>
> On Thu, Jan 29 2026 at 21:24, Prabhakar Lad wrote:
> > On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@kernel.org> wrote:
> >>
> >> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> >> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >> >
> >> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> >> > that allows software to explicitly assert interrupts toward individual
> >> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> >> > interrupt.
> >> >
> >> > Introduce a debug mechanism to trigger software interrupts on individual
> >> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> >> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> >> > explicitly enabled.
> >>
> >> Can't you reuse/extend the existing mechanism provided by
> >> CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
> >> instead of implementing yet another ad hoc debugfs magic?
> >>
> > Can you please point me to a driver which makes use of it? In my case
> > the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
> > ICU_SWINT.
>
> Care to look what irq_inject_interrupt() does?
>
> It tries first to inject the interrupt via irq_set_irqchip_state(),
> which only works when a chip in the hierarchy implements the
> chip::irq_set_irqchip_state() callback.
>
I did implement irq_set_irqchip_state but it doesn't land in the
rzv2h_icu_irq_set_irqchip_state(). So I was wondering if I missed
something.

#Trigger int-ca55-0
root@rzv2h-evk:/sys/kernel/debug/irq/irqs# echo trigger > 14

#The trace looks like below:
irq_debug_write()
  -> irq_inject_interrupt()
     -> irq_set_irqchip_state()

This lands in GICV3. For the RZ/V2H ICU only interrupts port_irqx and
tintx interrupts are registered  in irq_domain_create_hierarchy() for
the rest of the interrupts these are supposed to be directly handled
by GICv3.

root@rzv2h-evk:/sys/kernel/debug/irq/irqs# cat /proc/interrupts | grep
interr | grep 294
 14:          1          0          0          0    GICv3 294 Edge
 10400000.interrupt-controller
root@rzv2h-evk:/sys/kernel/debug/irq/irqs# cat 14
handler:  handle_fasteoi_irq
device:   (null)
status:   0x00000001
istate:   0x00004000
ddepth:   0
wdepth:   0
dstate:   0x0b400201
            IRQ_TYPE_EDGE_RISING
            IRQD_ACTIVATED
            IRQD_IRQ_STARTED
            IRQD_SINGLE_TARGET
            IRQD_DEFAULT_TRIGGER_SET
            IRQD_HANDLE_ENFORCE_IRQCTX
node:     -1
affinity: 0-3
effectiv: 0
domain:  :soc:interrupt-controller@14900000-1
 hwirq:   0x126
 chip:    GICv3
  flags:   0x15
             IRQCHIP_SET_TYPE_MASKED
             IRQCHIP_MASK_ON_SUSPEND
             IRQCHIP_SKIP_SET_WAKE

How do you propose to handle this? irq_inject_interrupt() would work
if I move int-ca55-x and icu-error-ca55 under
irq_domain_create_hierarchy().

Cheers,
Prabhakar

Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Thomas Gleixner]

On Fri, Jan 30 2026 at 11:17, Lad, Prabhakar wrote:
> On Thu, Jan 29, 2026 at 9:59 PM Thomas Gleixner <tglx@kernel.org> wrote:
>> It tries first to inject the interrupt via irq_set_irqchip_state(),
>> which only works when a chip in the hierarchy implements the
>> chip::irq_set_irqchip_state() callback.
>>
> I did implement irq_set_irqchip_state but it doesn't land in the
> rzv2h_icu_irq_set_irqchip_state(). So I was wondering if I missed
> something.
>
> #Trigger int-ca55-0
> root@rzv2h-evk:/sys/kernel/debug/irq/irqs# echo trigger > 14
>
> #The trace looks like below:
> irq_debug_write()
>   -> irq_inject_interrupt()
>      -> irq_set_irqchip_state()
>
> This lands in GICV3. For the RZ/V2H ICU only interrupts port_irqx and
> tintx interrupts are registered  in irq_domain_create_hierarchy() for
> the rest of the interrupts these are supposed to be directly handled
> by GICv3.
...
> How do you propose to handle this? irq_inject_interrupt() would work
> if I move int-ca55-x and icu-error-ca55 under
> irq_domain_create_hierarchy().

Correct. That's how the hierarchy works.

Re: [PATCH 5/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger

[Lad, Prabhakar]

Hi  Thomas,

On Mon, Jan 26, 2026 at 4:11 PM Thomas Gleixner <tglx@kernel.org> wrote:
>
> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
> > ECC RAM, and CA55/IP error conditions during bring-up and debugging.
>
> Why is that only relevant to bring-up and debugging? Those errors
> can't happen in production, right?
>
The error conditions can happen in production too. So I'll enable them
by default and drop the debug module param.

Cheers,
Prabhakar