From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Shiji Yang <yangshiji66@outlook.com>
Cc: linux-mtd@lists.infradead.org,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] mtd: spi-nor: swp: check SR_TB flag when getting tb_mask
Date: Wed, 28 Jan 2026 15:11:17 +0100 [thread overview]
Message-ID: <87bjidn7y2.fsf@bootlin.com> (raw)
In-Reply-To: <TYRPR01MB135884849485DE52A81D94965BC91A@TYRPR01MB13588.jpnprd01.prod.outlook.com> (Shiji Yang's message of "Wed, 28 Jan 2026 20:42:56 +0800")
On 28/01/2026 at 20:42:56 +08, Shiji Yang <yangshiji66@outlook.com> wrote:
> When the chip does not support top/bottom block protect, the tb_mask
> must be set to 0, otherwise SR1 bit5 will be unexpectedly modified.
>
> Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Good point.
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thanks,
Miquèl
next prev parent reply other threads:[~2026-01-28 14:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 12:42 [PATCH] mtd: spi-nor: swp: check SR_TB flag when getting tb_mask Shiji Yang
2026-01-28 14:11 ` Miquel Raynal [this message]
2026-02-09 10:31 ` Michael Walle
2026-03-13 11:15 ` Pratyush Yadav
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