[PATCH 0/7] irqchip: Adjust LoongArch irqchip drivers for 32BIT/64BIT

[PATCH 0/7] irqchip: Adjust LoongArch irqchip drivers for 32BIT/64BIT

[Huacai Chen]

Linux-6.19 adds basic LoongArch32 support:
https://git.kernel.org/torvalds/c/9551a26f17d9445eed497bd7c639d48dfc3c0af4

On the basis, this series adjust the LoongArch-specific irqchip drivers
for both 32BIT and 64BIT.

Jiaxun Yang & Huacai Chen (7):
 irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT.
 irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT.
 irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT.
 irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT.
 irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT.
 irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT.
 irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/Kconfig                | 11 +++++------
 drivers/irqchip/irq-loongarch-avec.c   | 14 +++++++------
 drivers/irqchip/irq-loongson-eiointc.c | 36 ++++++++++++++++++++++++++++------
 drivers/irqchip/irq-loongson-htvec.c   |  6 +++---
 drivers/irqchip/irq-loongson-liointc.c |  5 +++--
 drivers/irqchip/irq-loongson-pch-msi.c |  7 ++++---
 drivers/irqchip/irq-loongson-pch-pic.c |  7 ++++---
 7 files changed, 57 insertions(+), 29 deletions(-)
---
2.27.0

[PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

csr_read64() is only available on 64BIT LoongArch platform, so use
recently added adaptive csr_read() instead, so as to make the driver
work on both 32BIT and 64BIT platform.

BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT
platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongarch-avec.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loongarch-avec.c
index ba556c008cf3..fb8efde95393 100644
--- a/drivers/irqchip/irq-loongarch-avec.c
+++ b/drivers/irqchip/irq-loongarch-avec.c
@@ -58,11 +58,13 @@ struct avecintc_data {
 
 static inline void avecintc_enable(void)
 {
+#ifdef CONFIG_MACH_LOONGSON64
 	u64 value;
 
 	value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
 	value |= IOCSR_MISC_FUNC_AVEC_EN;
 	iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
+#endif
 }
 
 static inline void avecintc_ack_irq(struct irq_data *d)
@@ -167,7 +169,7 @@ void complete_irq_moving(void)
 	struct pending_list *plist = this_cpu_ptr(&pending_list);
 	struct avecintc_data *adata, *tdata;
 	int cpu, vector, bias;
-	uint64_t isr;
+	unsigned long isr;
 
 	guard(raw_spinlock)(&loongarch_avec.lock);
 
@@ -177,16 +179,16 @@ void complete_irq_moving(void)
 		bias = vector / VECTORS_PER_REG;
 		switch (bias) {
 		case 0:
-			isr = csr_read64(LOONGARCH_CSR_ISR0);
+			isr = csr_read(LOONGARCH_CSR_ISR0);
 			break;
 		case 1:
-			isr = csr_read64(LOONGARCH_CSR_ISR1);
+			isr = csr_read(LOONGARCH_CSR_ISR1);
 			break;
 		case 2:
-			isr = csr_read64(LOONGARCH_CSR_ISR2);
+			isr = csr_read(LOONGARCH_CSR_ISR2);
 			break;
 		case 3:
-			isr = csr_read64(LOONGARCH_CSR_ISR3);
+			isr = csr_read(LOONGARCH_CSR_ISR3);
 			break;
 		}
 
@@ -234,7 +236,7 @@ static void avecintc_irq_dispatch(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 
 	while (true) {
-		unsigned long vector = csr_read64(LOONGARCH_CSR_IRR);
+		unsigned long vector = csr_read(LOONGARCH_CSR_IRR);
 		if (vector & IRR_INVALID_MASK)
 			break;
 
-- 
2.47.3

[PATCH 2/7] irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type.
Currently we pass acpi_liointc->address to it. This can only work on
64BIT platform because its type is u64, so cast it to phys_addr_t and
then the driver works on both 32BIT and 64BIT platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-liointc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 0033c2188abc..f001a34878ba 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -394,8 +394,9 @@ static int __init acpi_cascade_irqdomain_init(void)
 
 int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc)
 {
-	int ret;
+	phys_addr_t addr = acpi_liointc->address;
 	struct fwnode_handle *domain_handle;
+	int ret;
 
 	parent_int_map[0] = acpi_liointc->cascade_map[0];
 	parent_int_map[1] = acpi_liointc->cascade_map[1];
@@ -403,7 +404,7 @@ int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic
 	parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]);
 	parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]);
 
-	domain_handle = irq_domain_alloc_fwnode(&acpi_liointc->address);
+	domain_handle = irq_domain_alloc_fwnode(&addr);
 	if (!domain_handle) {
 		pr_err("Unable to allocate domain handle\n");
 		return -ENOMEM;
-- 
2.47.3

[PATCH 3/7] irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

iocsr_read64()/iocsr_write64() are only available on 64BIT LoongArch
platform, so add and use a pair of helpers, i.e. read_isr()/write_isr()
instead, so as to make the driver work on both 32BIT and 64BIT platform.

BTW, make eiointc_enable() be a no-op since it is only needed by 64BIT
platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-eiointc.c | 36 +++++++++++++++++++++-----
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
index ad2105685b48..e2eb4cd27f78 100644
--- a/drivers/irqchip/irq-loongson-eiointc.c
+++ b/drivers/irqchip/irq-loongson-eiointc.c
@@ -37,9 +37,9 @@
 #define  EXTIOI_ENABLE_INT_ENCODE      BIT(2)
 #define  EXTIOI_ENABLE_CPU_ENCODE      BIT(3)
 
-#define VEC_REG_COUNT		4
-#define VEC_COUNT_PER_REG	64
-#define VEC_COUNT		(VEC_REG_COUNT * VEC_COUNT_PER_REG)
+#define VEC_COUNT		256
+#define VEC_COUNT_PER_REG	BITS_PER_LONG
+#define VEC_REG_COUNT		(VEC_COUNT / BITS_PER_LONG)
 #define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
 #define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
 #define EIOINTC_ALL_ENABLE	0xffffffff
@@ -85,11 +85,13 @@ static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
 
 static void eiointc_enable(void)
 {
+#ifdef CONFIG_MACH_LOONGSON64
 	uint64_t misc;
 
 	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
 	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
 	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
+#endif
 }
 
 static int cpu_to_eio_node(int cpu)
@@ -281,12 +283,34 @@ static int eiointc_router_init(unsigned int cpu)
 	return 0;
 }
 
+#if VEC_COUNT_PER_REG == 32
+static unsigned long read_isr(int i)
+{
+	return iocsr_read32(EIOINTC_REG_ISR + (i << 2));
+}
+
+static void write_isr(int i, unsigned long val)
+{
+	iocsr_write32(val, EIOINTC_REG_ISR + (i << 2));
+}
+#else
+static unsigned long read_isr(int i)
+{
+	return iocsr_read64(EIOINTC_REG_ISR + (i << 3));
+}
+
+static void write_isr(int i, unsigned long val)
+{
+	iocsr_write64(val, EIOINTC_REG_ISR + (i << 3));
+}
+#endif
+
 static void eiointc_irq_dispatch(struct irq_desc *desc)
 {
 	struct eiointc_ip_route *info = irq_desc_get_handler_data(desc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	bool handled = false;
-	u64 pending;
+	unsigned long pending;
 	int i;
 
 	chained_irq_enter(chip, desc);
@@ -299,14 +323,14 @@ static void eiointc_irq_dispatch(struct irq_desc *desc)
 	 * read ISR for these 64 interrupt vectors rather than all vectors
 	 */
 	for (i = info->start; i < info->end; i++) {
-		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
+		pending = read_isr(i);
 
 		/* Skip handling if pending bitmap is zero */
 		if (!pending)
 			continue;
 
 		/* Clear the IRQs */
-		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
+		write_isr(i, pending);
 		while (pending) {
 			int bit = __ffs(pending);
 			int irq = bit + VEC_COUNT_PER_REG * i;
-- 
2.47.3

[PATCH 4/7] irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type.
Currently we pass acpi_htvec->address to it. This can only work on 64BIT
platform because its type is u64, so cast it to phys_addr_t and then the
driver works on both 32BIT and 64BIT platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-htvec.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index d2be8e954e92..03c3992b39c8 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -298,8 +298,8 @@ static int __init acpi_cascade_irqdomain_init(void)
 int __init htvec_acpi_init(struct irq_domain *parent,
 				   struct acpi_madt_ht_pic *acpi_htvec)
 {
-	int i, ret;
-	int num_parents, parent_irq[8];
+	int i, ret, num_parents, parent_irq[8];
+	phys_addr_t addr = acpi_htvec->address;
 	struct fwnode_handle *domain_handle;
 
 	if (!acpi_htvec)
@@ -307,7 +307,7 @@ int __init htvec_acpi_init(struct irq_domain *parent,
 
 	num_parents = HTVEC_MAX_PARENT_IRQ;
 
-	domain_handle = irq_domain_alloc_fwnode(&acpi_htvec->address);
+	domain_handle = irq_domain_alloc_fwnode(&addr);
 	if (!domain_handle) {
 		pr_err("Unable to allocate domain handle\n");
 		return -ENOMEM;
-- 
2.47.3

[PATCH 5/7] irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type.
Currently we pass acpi_pchmsi->msg_address to it. This can only work on
64BIT platform because its type is u64, so cast it to phys_addr_t and
then the driver works on both 32BIT and 64BIT platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-pch-msi.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
index 4aedc9b90ff7..8500662bdb33 100644
--- a/drivers/irqchip/irq-loongson-pch-msi.c
+++ b/drivers/irqchip/irq-loongson-pch-msi.c
@@ -263,11 +263,12 @@ struct fwnode_handle *get_pch_msi_handle(int pci_segment)
 
 int __init pch_msi_acpi_init(struct irq_domain *parent, struct acpi_madt_msi_pic *acpi_pchmsi)
 {
-	int ret;
+	phys_addr_t msg_address = acpi_pchmsi->msg_address;
 	struct fwnode_handle *domain_handle;
+	int ret;
 
-	domain_handle = irq_domain_alloc_fwnode(&acpi_pchmsi->msg_address);
-	ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
+	domain_handle = irq_domain_alloc_fwnode(&msg_address);
+	ret = pch_msi_init(msg_address, acpi_pchmsi->start,
 				acpi_pchmsi->count, parent, domain_handle);
 	if (ret < 0)
 		irq_domain_free_fwnode(domain_handle);
-- 
2.47.3

[PATCH 6/7] irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type.
Currently we pass acpi_pchpic->address to it. This can only work on
64BIT platform because its type is u64, so cast it to phys_addr_t and
then the driver works on both 32BIT and 64BIT platform.

BTW, use readl() to get vec_count because readq() is only available on
64BIT platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-pch-pic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index c6b369a974a7..2ac7e3245b72 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -343,7 +343,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base,
 		priv->table[i] = PIC_UNDEF_VECTOR;
 
 	priv->ht_vec_base = vec_base;
-	priv->vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
+	priv->vec_count = ((readl(priv->base + 4) >> 16) & 0xff) + 1;
 	priv->gsi_base = gsi_base;
 
 	priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
@@ -449,13 +449,14 @@ static int __init acpi_cascade_irqdomain_init(void)
 int __init pch_pic_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_bio_pic *acpi_pchpic)
 {
-	int ret;
+	phys_addr_t addr = acpi_pchpic->address;
 	struct fwnode_handle *domain_handle;
+	int ret;
 
 	if (find_pch_pic(acpi_pchpic->gsi_base) >= 0)
 		return 0;
 
-	domain_handle = irq_domain_alloc_fwnode(&acpi_pchpic->address);
+	domain_handle = irq_domain_alloc_fwnode(&addr);
 	if (!domain_handle) {
 		pr_err("Unable to allocate domain handle\n");
 		return -ENOMEM;
-- 
2.47.3

[PATCH 7/7] irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT

[Huacai Chen]

All LoongArch irqchip drivers are adjusted, allow them be built on both
32BIT and 64BIT platforms.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/Kconfig | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f334f49c9791..270f1c4783e3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -698,7 +698,7 @@ config IRQ_LOONGARCH_CPU
 
 config LOONGSON_LIOINTC
 	bool "Loongson Local I/O Interrupt Controller"
-	depends on MACH_LOONGSON64
+	depends on MACH_LOONGSON64 || LOONGARCH
 	default y
 	select IRQ_DOMAIN
 	select GENERIC_IRQ_CHIP
@@ -708,7 +708,6 @@ config LOONGSON_LIOINTC
 config LOONGSON_EIOINTC
 	bool "Loongson Extend I/O Interrupt Controller"
 	depends on LOONGARCH
-	depends on MACH_LOONGSON64
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
 	select GENERIC_IRQ_CHIP
@@ -726,7 +725,7 @@ config LOONGSON_HTPIC
 
 config LOONGSON_HTVEC
 	bool "Loongson HyperTransport Interrupt Vector Controller"
-	depends on MACH_LOONGSON64
+	depends on MACH_LOONGSON64 || LOONGARCH
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
 	help
@@ -734,7 +733,7 @@ config LOONGSON_HTVEC
 
 config LOONGSON_PCH_PIC
 	bool "Loongson PCH PIC Controller"
-	depends on MACH_LOONGSON64
+	depends on MACH_LOONGSON64 || LOONGARCH
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
 	select IRQ_FASTEOI_HIERARCHY_HANDLERS
@@ -743,7 +742,7 @@ config LOONGSON_PCH_PIC
 
 config LOONGSON_PCH_MSI
 	bool "Loongson PCH MSI Controller"
-	depends on MACH_LOONGSON64
+	depends on MACH_LOONGSON64 || LOONGARCH
 	depends on PCI
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
@@ -755,7 +754,7 @@ config LOONGSON_PCH_MSI
 config LOONGSON_PCH_LPC
 	bool "Loongson PCH LPC Controller"
 	depends on LOONGARCH
-	depends on MACH_LOONGSON64
+	depends on MACH_LOONGSON64 || LOONGARCH
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
 	help
-- 
2.47.3

Re: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

[Thomas Gleixner]

On Tue, Dec 23 2025 at 16:04, Huacai Chen wrote:

> csr_read64() is only available on 64BIT LoongArch platform, so use
> recently added adaptive csr_read() instead, so as to make the driver
> work on both 32BIT and 64BIT platform.
>
> BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT
> platform.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

I assume Jiaxun is the author, which means that this lacks a

  From: Jiaxun

line in the mail body before the change log starts. Please try again.

>  static inline void avecintc_enable(void)
>  {
> +#ifdef CONFIG_MACH_LOONGSON64
>  	u64 value;
>  
>  	value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>  	value |= IOCSR_MISC_FUNC_AVEC_EN;
>  	iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
> +#endif

Can't this be:

      if (IS_ENABLED(CONFIG_MACH_LOONGSON64))

which is preferred over ifdeffery?

Thanks,

        tglx

Re: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

[Jiaxun Yang]

On Fri, 9 Jan 2026, at 12:09 PM, Thomas Gleixner wrote:
> On Tue, Dec 23 2025 at 16:04, Huacai Chen wrote:
>
>> csr_read64() is only available on 64BIT LoongArch platform, so use
>> recently added adaptive csr_read() instead, so as to make the driver
>> work on both 32BIT and 64BIT platform.
>>
>> BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT
>> platform.
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>
> I assume Jiaxun is the author, which means that this lacks a
>
>   From: Jiaxun
>
> line in the mail body before the change log starts. Please try again.

Yes, Huacai could you please get it fixed?

>
>>  static inline void avecintc_enable(void)
>>  {
>> +#ifdef CONFIG_MACH_LOONGSON64
>>  	u64 value;
>>  
>>  	value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>>  	value |= IOCSR_MISC_FUNC_AVEC_EN;
>>  	iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
>> +#endif
>
> Can't this be:
>
>       if (IS_ENABLED(CONFIG_MACH_LOONGSON64))
>
> which is preferred over ifdeffery?

Sadly, iocsr_read64 symbol is only available on 64 bit systems,
so it must be guarded somehow.

Thanks

>
> Thanks,
>
>         tglx

-- 
- Jiaxun

Re: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

[Thomas Gleixner]

On Fri, Jan 09 2026 at 12:23, Jiaxun Yang wrote:
> On Fri, 9 Jan 2026, at 12:09 PM, Thomas Gleixner wrote:
>>>  static inline void avecintc_enable(void)
>>>  {
>>> +#ifdef CONFIG_MACH_LOONGSON64
>>>  	u64 value;
>>>  
>>>  	value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>>>  	value |= IOCSR_MISC_FUNC_AVEC_EN;
>>>  	iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
>>> +#endif
>>
>> Can't this be:
>>
>>       if (IS_ENABLED(CONFIG_MACH_LOONGSON64))
>>
>> which is preferred over ifdeffery?
>
> Sadly, iocsr_read64 symbol is only available on 64 bit systems,
> so it must be guarded somehow.

It's unconditionally defined so using IS_ENABLED() is fine because the
compiler optimizes everything out before the resolv stage.

Thanks,

        tglx

Re: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

On Fri, Jan 9, 2026 at 8:09 PM Thomas Gleixner <tglx@kernel.org> wrote:
>
> On Tue, Dec 23 2025 at 16:04, Huacai Chen wrote:
>
> > csr_read64() is only available on 64BIT LoongArch platform, so use
> > recently added adaptive csr_read() instead, so as to make the driver
> > work on both 32BIT and 64BIT platform.
> >
> > BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT
> > platform.
> >
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>
> I assume Jiaxun is the author, which means that this lacks a
>
>   From: Jiaxun
>
> line in the mail body before the change log starts. Please try again.
We are co-developer, so I think

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

is appropriate.

>
> >  static inline void avecintc_enable(void)
> >  {
> > +#ifdef CONFIG_MACH_LOONGSON64
> >       u64 value;
> >
> >       value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> >       value |= IOCSR_MISC_FUNC_AVEC_EN;
> >       iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
> > +#endif
>
> Can't this be:
>
>       if (IS_ENABLED(CONFIG_MACH_LOONGSON64))
>
> which is preferred over ifdeffery?
OK, I will do it in the next version.

Huacai

>
> Thanks,
>
>         tglx
>

Re: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

[Huacai Chen]

On Sat, Jan 10, 2026 at 4:37 AM Thomas Gleixner <tglx@kernel.org> wrote:
>
> On Fri, Jan 09 2026 at 12:23, Jiaxun Yang wrote:
> > On Fri, 9 Jan 2026, at 12:09 PM, Thomas Gleixner wrote:
> >>>  static inline void avecintc_enable(void)
> >>>  {
> >>> +#ifdef CONFIG_MACH_LOONGSON64
> >>>     u64 value;
> >>>
> >>>     value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> >>>     value |= IOCSR_MISC_FUNC_AVEC_EN;
> >>>     iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
> >>> +#endif
> >>
> >> Can't this be:
> >>
> >>       if (IS_ENABLED(CONFIG_MACH_LOONGSON64))
> >>
> >> which is preferred over ifdeffery?
> >
> > Sadly, iocsr_read64 symbol is only available on 64 bit systems,
> > so it must be guarded somehow.
>
> It's unconditionally defined so using IS_ENABLED() is fine because the
> compiler optimizes everything out before the resolv stage.
I'm sorry but IS_ENABLED() doesn't work in this case. Because
iocsr_read64() is not a regular function but a compiler intrinsic, it
is handled in the pre-process stage, so still causes build errors.

Please ignore my V2 and I will re-send V3, thanks.

Huacai

>
> Thanks,
>
>         tglx