From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52FA81798F; Fri, 12 Sep 2025 21:46:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757713587; cv=none; b=GfkebnmEeDQ9Tve99TkgAHZSzBqKOHnUm91x2k9I7hxEj58oyUOzgKLCJtXKrTANJoN0pbUz0IoP/mMWpkXcimt050BhCMovlkw5Y/5myajDJfFTgyYKFvIQlZgoeA+klW7sE3JFSDJGoEM3cylQTRyuyfzy6DocgDksaQobFFg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757713587; c=relaxed/simple; bh=LE/pKOZjl39+pd41X1ZUViQqZVkvkaULc0/s+XUleLM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=qba525/gFjVbvYCIPQ8e/I9zHsHoMyg5WG5yfoil9MsK6P70SiE0CVQmcoB6aEF7f6cs8S+tM6F/deFzdrWOWxAm/GYsOXZQ+plYsdeKuO/AZ9RKNFnslnms8rAR/V8IPMKP/N8U5INmgqpBRgS+KDsqFxyk032OIdTyeukI748= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vg8ENwcS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vg8ENwcS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D47F8C4CEF1; Fri, 12 Sep 2025 21:46:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757713586; bh=LE/pKOZjl39+pd41X1ZUViQqZVkvkaULc0/s+XUleLM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Vg8ENwcSM/0SbWBZCbjFFP2ze6ITCVRYLRkQzz1Vxr4GlnSTxb9plxsUwaJD1Z4ER DaJKDUOGVo3ytea8MNLu0g66lEck4hPQv8IPnhO5P49qKQybUVUaZ0rzurlgPWkKje TXepy2qTBZ4Sf4/KBC2FxpY/1Oo5f+B8YEV+dferDgflFqKw8RPsScXkMj2Esk1AAe GOiH2nsIN8KV7d6dIPbk5g6S9Z8uu0RZOPat05zfRK3xvolfSDDiu6uUwMHp7WCDHY x1s3m4I9FOn78LOeQ1quboX3Jn+99BdpLXOWN/GBR9zOJKbv08tUryVe3I3dJLD6Fi CZgzBAxhwVCdQ== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1uxBb6-00000005pVz-3V5f; Fri, 12 Sep 2025 21:46:24 +0000 Date: Fri, 12 Sep 2025 22:46:23 +0100 Message-ID: <87bjnfz6mo.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Thiago Jung Bauermann Subject: Re: [PATCH v16 6/6] KVM: selftests: arm64: Add GCS registers to get-reg-list In-Reply-To: <20250912-arm64-gcs-v16-6-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> <20250912-arm64-gcs-v16-6-6435e5ec37db@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, thiago.bauermann@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 12 Sep 2025 10:25:32 +0100, Mark Brown wrote: > > GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add > these to those validated by get-reg-list. > > Reviewed-by: Thiago Jung Bauermann > Signed-off-by: Mark Brown > --- > tools/testing/selftests/kvm/arm64/get-reg-list.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testing/selftests/kvm/arm64/get-reg-list.c > index 011fad95dd02..9bf33064377b 100644 > --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c > +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c > @@ -42,6 +42,12 @@ struct feature_id_reg { > static struct feature_id_reg feat_id_regs[] = { > REG_FEAT(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), > REG_FEAT(TCR2_EL2, ID_AA64MMFR3_EL1, TCRX, IMP), > + REG_FEAT(GCSPR_EL0, ID_AA64PFR1_EL1, GCS, IMP), > + REG_FEAT(GCSPR_EL1, ID_AA64PFR1_EL1, GCS, IMP), > + REG_FEAT(GCSPR_EL2, ID_AA64PFR1_EL1, GCS, IMP), > + REG_FEAT(GCSCRE0_EL1, ID_AA64PFR1_EL1, GCS, IMP), > + REG_FEAT(GCSCR_EL1, ID_AA64PFR1_EL1, GCS, IMP), > + REG_FEAT(GCSCR_EL2, ID_AA64PFR1_EL1, GCS, IMP), > REG_FEAT(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), > REG_FEAT(PIRE0_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), > REG_FEAT(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), > @@ -486,6 +492,9 @@ static __u64 base_regs[] = { > ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ > ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ > ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ > + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ > + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ > + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ > ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ > ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ > ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ > @@ -502,6 +511,7 @@ static __u64 base_regs[] = { > ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ > ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ > ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ > + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ > ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ > ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ > ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ > @@ -740,6 +750,8 @@ static __u64 el2_regs[] = { > SYS_REG(PIRE0_EL2), > SYS_REG(PIR_EL2), > SYS_REG(POR_EL2), > + SYS_REG(GCSPR_EL2), > + SYS_REG(GCSCR_EL2), > SYS_REG(AMAIR_EL2), > SYS_REG(VBAR_EL2), > SYS_REG(CONTEXTIDR_EL2), > More importantly, I'd expect a test that exercises the exception paths, as the current code is pretty broken. M. -- Jazz isn't dead. It just smells funny.