From: Thomas Gleixner <tglx@linutronix.de>
To: Sohil Mehta <sohil.mehta@intel.com>, LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Tom Lendacky <thomas.lendacky@amd.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Huang Rui <ray.huang@amd.com>, Juergen Gross <jgross@suse.com>,
Dimitri Sivanich <dimitri.sivanich@hpe.com>,
Michael Kelley <mikelley@microsoft.com>,
K Prateek Nayak <kprateek.nayak@amd.com>,
Kan Liang <kan.liang@linux.intel.com>,
Zhang Rui <rui.zhang@intel.com>,
"Paul E. McKenney" <paulmck@kernel.org>,
Feng Tang <feng.tang@intel.com>,
Andy Shevchenko <andy@infradead.org>
Subject: Re: [patch 00/53] x86/topology: The final installment
Date: Tue, 08 Aug 2023 22:57:31 +0200 [thread overview]
Message-ID: <87bkfhl0as.ffs@tglx> (raw)
In-Reply-To: <7ef60626-28ab-a4cc-2f24-4f35e3d946aa@intel.com>
On Tue, Aug 08 2023 at 13:30, Sohil Mehta wrote:
> On 8/8/2023 12:10 PM, Thomas Gleixner wrote:
> domain: Thread shift: 1 dom_size: 2 max_threads: 2
> domain: Core shift: 5 dom_size: 16 max_threads: 32
> domain: Module shift: 5 dom_size: 1 max_threads: 32
> domain: Tile shift: 5 dom_size: 1 max_threads: 32
> domain: Die shift: 5 dom_size: 1 max_threads: 32
> domain: Package shift: 5 dom_size: 1 max_threads: 32
>
> CPU 0:
> 0x0000000b 0x00: eax=0x00000001 ebx=0x00000002 ecx=0x00000100 edx=0x00000000
> 0x0000000b 0x01: eax=0x00000005 ebx=0x00000014 ecx=0x00000201 edx=0x00000000
Ok. So this is consistent.
> Also, I see a warning message that only seems to show up with the final
> installment series applied. I attached the complete dmesg as well (just
> in case):
>
> unchecked MSR access error: WRMSR to 0xe44 (tried to write
> 0x0000000000000003) at rIP: 0xffffffff8d2a6698 (native_write_msr+0x8/0x30)
> uncore_box_ref.part.0+0xa6/0xe0
> uncore_event_cpu_online+0x6e/0x1c0
> ? __pfx_uncore_event_cpu_online+0x10/0x10
> cpuhp_invoke_callback+0x165/0x4b0
That's probably a consequence of the inconsistency.
> [ 0.187210] CPU topo: Register 000 1
> [ 0.187211] CPU topo: Register 002 1
> [ 0.187212] CPU topo: Register 004 1
> [ 0.187213] CPU topo: Register 006 1
> [ 0.187214] CPU topo: Register 008 1
> [ 0.187215] CPU topo: Register 010 1
> [ 0.187216] CPU topo: Register 012 1
> [ 0.187217] CPU topo: Register 014 1
> [ 0.187218] CPU topo: Register 016 1
> [ 0.187219] CPU topo: Register 018 1
The first package (primary threads)
> [ 0.187219] CPU topo: Register 020 1
> [ 0.187220] CPU topo: Register 022 1
> [ 0.187221] CPU topo: Register 024 1
> [ 0.187222] CPU topo: Register 026 1
> [ 0.187223] CPU topo: Register 028 1
> [ 0.187223] CPU topo: Register 030 1
> [ 0.187224] CPU topo: Register 032 1
> [ 0.187225] CPU topo: Register 034 1
> [ 0.187226] CPU topo: Register 036 1
> [ 0.187227] CPU topo: Register 038 1
The second package (primary threads)
> [ 0.187228] CPU topo: Register 001 1
> [ 0.187228] CPU topo: Register 003 1
> [ 0.187229] CPU topo: Register 005 1
> [ 0.187230] CPU topo: Register 007 1
> [ 0.187230] CPU topo: Register 009 1
> [ 0.187231] CPU topo: Register 011 1
> [ 0.187232] CPU topo: Register 013 1
> [ 0.187233] CPU topo: Register 015 1
> [ 0.187233] CPU topo: Register 017 1
> [ 0.187234] CPU topo: Register 019 1
The second package (secondary threads)
> [ 0.187235] CPU topo: Register 021 1
> [ 0.187235] CPU topo: Register 023 1
> [ 0.187236] CPU topo: Register 025 1
> [ 0.187237] CPU topo: Register 027 1
> [ 0.187238] CPU topo: Register 029 1
> [ 0.187238] CPU topo: Register 031 1
> [ 0.187239] CPU topo: Register 033 1
> [ 0.187240] CPU topo: Register 035 1
> [ 0.187241] CPU topo: Register 037 1
> [ 0.187241] CPU topo: Register 039 1
The second package (secondary threads)
> [ 0.187244] CPU topo: Register 000 0
> [ 0.187244] CPU topo: Register 001 0
... PKG 0
> [ 0.187266] CPU topo: Register 01e 0
> [ 0.187267] CPU topo: Register 01f 0
Ah. that's indeed the issue which the ACPI patch addresses. So that
table claims that the packages are truly filled up to capacity, i.e. 32
threads. The old code did not notice because they are all marked
non-present, but with the new approach these are rightfully accounted as
pluggable and show up in the bitmaps accordingly. Sigh...
> [ 0.187268] CPU topo: Register 020 0
... PKG 1
> [ 0.187291] CPU topo: Register 03f 0
> [ 0.187292] CPU topo: Register 040 0
... PKG 2
> [ 0.187304] CPU topo: Register 05f 0
> [ 0.187305] CPU topo: Register 060 0
... PKG 3
> [ 0.187335] CPU topo: Register 077 0
This one is funny as it stops at 0x77, i.e 8 CPUs short of the full
range.
So this:
> [ 0.187412] CPU topo: Max. logical packages: 4
_IS_ correct according to the above.
I bet that the ACPI patch cures it.
Thanks,
tglx
next prev parent reply other threads:[~2023-08-08 21:00 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-07 13:52 [patch 00/53] x86/topology: The final installment Thomas Gleixner
2023-08-07 13:52 ` [patch 01/53] x86/cpu/topology: Cure off by one in fake_topology() Thomas Gleixner
2023-08-07 13:52 ` [patch 02/53] x86/cpu/topology: Make the APIC mismatch warnings complete Thomas Gleixner
2023-08-07 14:28 ` Arjan van de Ven
2023-08-07 14:54 ` Thomas Gleixner
2023-08-07 13:52 ` [patch 03/53] x86/platform/ce4100: Dont override x86_init.mpparse.setup_ioapic_ids Thomas Gleixner
2023-08-07 15:20 ` Andy Shevchenko
2023-08-07 13:52 ` [patch 04/53] x86/ioapic: Replace some more set bit nonsense Thomas Gleixner
2023-08-07 13:52 ` [patch 05/53] x86/apic: Get rid of get_physical_broadcast() Thomas Gleixner
2023-08-07 15:24 ` Andy Shevchenko
2023-08-07 13:52 ` [patch 06/53] x86/ioapic: Make io_apic_get_unique_id() simpler Thomas Gleixner
2023-08-07 13:52 ` [patch 07/53] x86/ioapic: Simplify setup_ioapic_ids_from_mpc_nocheck() Thomas Gleixner
2023-08-07 13:52 ` [patch 08/53] x86/apic: Remove check_apicid_used() and ioapic_phys_id_map() Thomas Gleixner
2023-08-07 13:52 ` [patch 09/53] x86/mpparse: Rename default_find_smp_config() Thomas Gleixner
2023-08-07 16:03 ` Andy Shevchenko
2023-08-07 17:21 ` Thomas Gleixner
2023-08-07 13:52 ` [patch 10/53] x86/mpparse: Provide separate early/late callbacks Thomas Gleixner
2023-08-07 13:52 ` [patch 11/53] x86/mpparse: Prepare for callback separation Thomas Gleixner
2023-08-07 13:52 ` [patch 12/53] x86/dtb: Rename x86_dtb_init() Thomas Gleixner
2023-08-07 13:52 ` [patch 13/53] x86/platform/ce4100: Prepare for separate mpparse callbacks Thomas Gleixner
2023-08-07 13:52 ` [patch 14/53] x86/platform/intel-mid: " Thomas Gleixner
2023-08-07 16:07 ` Andy Shevchenko
2023-08-07 13:52 ` [patch 15/53] x86/jailhouse: " Thomas Gleixner
2023-08-07 13:52 ` [patch 16/53] x86/xen/smp_pv: " Thomas Gleixner
2023-08-07 13:53 ` [patch 17/53] x86/mpparse: Switch to new init callbacks Thomas Gleixner
2023-08-07 13:53 ` [patch 18/53] x86/mm/numa: Move early mptable evaluation into common code Thomas Gleixner
2023-08-07 13:53 ` [patch 19/53] x86/mpparse: Remove the physid_t bitmap wrapper Thomas Gleixner
2023-08-08 11:37 ` Andy Shevchenko
2023-08-07 13:53 ` [patch 20/53] x86/apic: Remove the pointless writeback of boot_cpu_physical_apicid Thomas Gleixner
2023-08-07 13:53 ` [patch 21/53] x86/apic: Remove yet another dubious callback Thomas Gleixner
2023-08-07 13:53 ` [patch 22/53] x86/apic: Use a proper define for invalid ACPI CPU ID Thomas Gleixner
2023-08-07 13:53 ` [patch 23/53] x86/cpu/topology: Move registration out of APIC code Thomas Gleixner
2023-08-07 13:53 ` [patch 24/53] x86/cpu/topology: Provide separate APIC registration functions Thomas Gleixner
2023-08-11 12:32 ` Zhang, Rui
2023-08-07 13:53 ` [patch 25/53] x86/acpi: Use new " Thomas Gleixner
2023-08-07 15:27 ` Peter Zijlstra
2023-08-07 15:35 ` Andrew Cooper
2023-08-07 15:41 ` Thomas Gleixner
2023-08-07 13:53 ` [patch 26/53] x86/jailhouse: Use new APIC registration function Thomas Gleixner
2023-08-07 13:53 ` [patch 27/53] x86/of: Use new APIC registration functions Thomas Gleixner
2023-08-07 13:53 ` [patch 28/53] x86/mpparse: Use new APIC registration function Thomas Gleixner
2023-08-07 13:53 ` [patch 29/53] x86/acpi: Dont invoke topology_register_apic() for XEN PV Thomas Gleixner
2023-08-07 13:53 ` [patch 30/53] x86/xen/smp_pv: Register fake APICs Thomas Gleixner
2023-08-07 13:53 ` [patch 31/53] x86/cpu/topology: Confine topology information Thomas Gleixner
2023-08-07 13:53 ` [patch 32/53] x86/cpu/topology: Simplify APIC registration Thomas Gleixner
2023-08-07 13:53 ` [patch 33/53] x86/cpu/topology: Use a data structure for topology info Thomas Gleixner
2023-08-07 13:53 ` [patch 34/53] x86/smpboot: Make error message actually useful Thomas Gleixner
2023-08-07 13:53 ` [patch 35/53] x86/cpu/topology: Sanitize the APIC admission logic Thomas Gleixner
2023-08-07 13:53 ` [patch 36/53] x86/cpu/topology: Rework possible CPU management Thomas Gleixner
2023-08-14 8:29 ` Zhang, Rui
2023-08-07 13:53 ` [patch 37/53] x86/cpu: Detect real BSP on crash kernels Thomas Gleixner
2024-01-08 14:11 ` Zhang, Rui
2024-01-08 14:54 ` Thomas Gleixner
2024-01-08 16:13 ` Thomas Gleixner
2024-01-09 1:54 ` Zhang, Rui
2024-01-10 14:19 ` Thomas Gleixner
2024-01-10 15:14 ` Thomas Gleixner
2024-01-11 1:52 ` Zhang, Rui
2024-01-12 9:14 ` Zhang, Rui
2024-01-12 15:39 ` Thomas Gleixner
2024-01-13 7:35 ` Zhang, Rui
2024-01-15 9:41 ` Thomas Gleixner
2023-08-07 13:53 ` [patch 38/53] x86/topology: Add a mechanism to track topology via APIC IDs Thomas Gleixner
2023-08-07 13:53 ` [patch 39/53] x86/cpu/topology: Reject unknown APIC IDs on ACPI hotplug Thomas Gleixner
2023-08-07 13:53 ` [patch 40/53] x86/cpu/topology: Assign hotpluggable CPUIDs during init Thomas Gleixner
2023-08-07 13:53 ` [patch 41/53] x86/xen/smp_pv: Count number of vCPUs early Thomas Gleixner
2023-08-07 13:53 ` [patch 42/53] x86/cpu/topology: Let XEN/PV use topology from CPUID/MADT Thomas Gleixner
2023-08-07 13:53 ` [patch 43/53] x86/cpu/topology: Use topology bitmaps for sizing Thomas Gleixner
2023-08-07 13:53 ` [patch 44/53] x86/cpu/topology: Mop up primary thread mask handling Thomas Gleixner
2023-08-07 13:53 ` [patch 45/53] x86/cpu/topology: Simplify cpu_mark_primary_thread() Thomas Gleixner
2023-08-07 13:53 ` [patch 46/53] x86/cpu/topology: Provide logical pkg/die mapping Thomas Gleixner
2023-08-07 13:53 ` [patch 47/53] x86/cpu/topology: Use topology logical mapping mechanism Thomas Gleixner
2023-08-07 13:53 ` [patch 48/53] x86/cpu/topology: Retrieve cores per package from topology bitmaps Thomas Gleixner
2023-08-07 13:53 ` [patch 49/53] x86: Use topology functions instead of smp_num_siblings where applicable Thomas Gleixner
2023-08-07 13:53 ` [patch 50/53] x86/cpu/topology: Rename smp_num_siblings Thomas Gleixner
2023-08-07 13:53 ` [patch 51/53] x86/cpu/topology: Rename topology_max_die_per_package() Thomas Gleixner
2023-08-07 13:53 ` [patch 52/53] x86/cpu/topology: Provide __num_[cores|threads]_per_package Thomas Gleixner
2023-08-07 13:53 ` [patch 53/53] x86/cpu/topology: Get rid of cpuinfo::x86_max_cores Thomas Gleixner
2023-08-11 15:44 ` Zhang, Rui
2023-12-14 14:00 ` Zhang, Rui
2023-08-08 7:40 ` [patch 00/53] x86/topology: The final installment Juergen Gross
2023-08-08 11:20 ` Andrew Cooper
2023-08-08 18:55 ` Thomas Gleixner
2023-08-08 18:29 ` Sohil Mehta
2023-08-08 19:10 ` Thomas Gleixner
2023-08-08 20:30 ` Sohil Mehta
2023-08-08 20:41 ` Thomas Gleixner
2023-08-08 22:10 ` Peter Zijlstra
2023-08-08 22:58 ` Sohil Mehta
2023-08-08 23:20 ` Thomas Gleixner
2023-08-09 16:55 ` Sohil Mehta
2023-08-10 3:28 ` Zhang, Rui
2023-08-09 16:50 ` Qiuxu Zhuo
2023-08-09 17:23 ` Sohil Mehta
2023-08-10 1:33 ` Zhuo, Qiuxu
2023-08-08 20:57 ` Thomas Gleixner [this message]
2023-08-09 16:12 ` Qiuxu Zhuo
2023-08-12 13:51 ` Michael Kelley (LINUX)
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