From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0951CC77B7A for ; Tue, 16 May 2023 07:20:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230293AbjEPHUT (ORCPT ); Tue, 16 May 2023 03:20:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231428AbjEPHUK (ORCPT ); Tue, 16 May 2023 03:20:10 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 688AF18E for ; Tue, 16 May 2023 00:20:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EEA5C615F6 for ; Tue, 16 May 2023 07:20:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58500C433EF; Tue, 16 May 2023 07:20:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684221608; bh=G6W4gAaiotYAbVHprBxvdN6E0N9T8QsCSHK8E+42gFw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=AEb4aluCzaMUCmWPJJ8FQWfUVf1NqE9UA8AiRiHgFznv3jdvKKE0piD6BTYDKWaa4 wtvU8zucqtRKpDtTLFh6qOZWOrE80EvJhj29I+yvipKANuElrfL1p+z8vGrrSeCARZ o1zeV4G0Ctl5MgspifyUmoSOwB8IunC2Fba5xYzPw+bq70RD80E8jkfeYjwbHxouoj rxNaOGPsHC0qq4ldXddVSGA8p3UGzBiTHGhcJYcoUbWHzpbL+t3sw0R0y1uXcTLzpY h8ZP4Z9IdYVDxqlfJhoONt2FbXEo5GbTDz34kd5ymthcO9Sk+mUflq34g5v3pGjQPU TqdkEmUHgjApQ== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pyoyb-00FRqS-Og; Tue, 16 May 2023 08:20:06 +0100 Date: Tue, 16 May 2023 08:18:54 +0100 Message-ID: <87bkikwxpd.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Brown , linux-kernel@vger.kernel.org Subject: Re: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1 In-Reply-To: References: <20230515105328.239204-1-anshuman.khandual@arm.com> <86ilctn233.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 16 May 2023 03:43:27 +0100, Anshuman Khandual wrote: > > > > On 5/15/23 19:12, Marc Zyngier wrote: > > On Mon, 15 May 2023 11:53:28 +0100, > > Anshuman Khandual wrote: > >> [...] > >> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > >> index 037724b19c5c..06bf321a17be 100644 > >> --- a/arch/arm64/include/asm/el2_setup.h > >> +++ b/arch/arm64/include/asm/el2_setup.h > >> @@ -161,6 +161,16 @@ > >> msr_s SYS_HFGWTR_EL2, x0 > >> msr_s SYS_HFGITR_EL2, xzr > >> > >> + mrs x1, id_aa64dfr0_el1 > >> + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 > >> + cbz x1, .Lskip_brbe_\@ > >> + > >> + mov x0, xzr > >> + orr x0, x0, #HFGITR_EL2_nBRBIALL > >> + orr x0, x0, #HFGITR_EL2_nBRBINJ > >> + msr_s SYS_HFGITR_EL2, x0 > > > > This will break badly if someone inserts something between this hunk > > and the initial setting of HFGITR_EL2. I'd really prefer a RMW > > approach. It's not that this code has to be optimised anyway. > > Something like this instead ? So that even if there are more changes > before this hunk, it will be fetched correctly with first mrs_s and > only additional bits related to BRBE will be set there after. > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index 037724b19c5c..bfaf41ad9c4e 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -161,6 +161,16 @@ > msr_s SYS_HFGWTR_EL2, x0 > msr_s SYS_HFGITR_EL2, xzr > > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 > + cbz x1, .Lskip_brbe_\@ > + > + mrs_s x0, SYS_HFGITR_EL2 > + orr x0, x0, #HFGITR_EL2_nBRBIALL > + orr x0, x0, #HFGITR_EL2_nBRBINJ > + msr_s SYS_HFGITR_EL2, x0 > + > +.Lskip_brbe_\@: > mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU > ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 > cbz x1, .Lskip_fgt_\@ Yes, this is much better. M. -- Without deviation from the norm, progress is not possible.