From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5954C433F5 for ; Mon, 21 Feb 2022 10:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355211AbiBUKqZ (ORCPT ); Mon, 21 Feb 2022 05:46:25 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355230AbiBUKpm (ORCPT ); Mon, 21 Feb 2022 05:45:42 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEF9762F8 for ; Mon, 21 Feb 2022 02:06:36 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1107460C11 for ; Mon, 21 Feb 2022 10:06:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7906BC340E9; Mon, 21 Feb 2022 10:06:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645437995; bh=EAg8qRnojnOG9Klcio4JVQSoeMM7BiVD8rhDZqhOPTA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=V/GH8/s4qiWDxM0W3kR+h/+jjuT+XDRZJzuf8NykEjP8KSWvnR/dKOakQBwy/O+w/ 7DItrH5EcNbUmMmrpWkAOKVtKwLpdL3DcKZv4dwslR5YZTn91eXlyp6IJAgjgfXUsU ZOsm/7HIsELjXGT5ZGUH/CYEtZMZjgsTIEX1CQC9ASvqjApHwukq1HPtFcQQeU1OFL o8DyNv/qJwJNgOkKWzxSQHr6aw0P/jV+hBUpXeT7YYQvPBQAKozfEG57abiVgH5nC7 ussqV3e0XFqgRC2JrA2R6nYdGrsF58WTZeH2v3/DJNHvGGge+z1eyGzK1yzFmrkCUQ UXJXxlUbxZ6Aw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nM5aT-009FuI-J8; Mon, 21 Feb 2022 10:06:33 +0000 Date: Mon, 21 Feb 2022 10:06:33 +0000 Message-ID: <87bkz04jpy.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" Subject: Re: [PATCH v3 2/6] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode In-Reply-To: References: <20220220050854.743420-1-apatel@ventanamicro.com> <20220220050854.743420-3-apatel@ventanamicro.com> <87czjg4kf4.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, daniel.lezcano@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Feb 2022 09:55:05 +0000, Anup Patel wrote: > > On Mon, Feb 21, 2022 at 3:21 PM Marc Zyngier wrote: > > > > On Sun, 20 Feb 2022 05:08:50 +0000, > > Anup Patel wrote: > > > > > > Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and > > > KVM RISC-V) don't have associated DT node but these drivers need > > > standard per-CPU (local) interrupts defined by the RISC-V privileged > > > specification. > > > > > > We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V > > > drivers not having DT node to discover INTC hwnode which in-turn > > > helps these drivers to map per-CPU (local) interrupts provided > > > by the INTC driver. > > > > > > Signed-off-by: Anup Patel > > > --- > > > arch/riscv/include/asm/irq.h | 4 ++++ > > > arch/riscv/kernel/irq.c | 19 +++++++++++++++++++ > > > drivers/irqchip/irq-riscv-intc.c | 7 +++++++ > > > 3 files changed, 30 insertions(+) > > > [...] > > > index b65bd8878d4f..fa24ecd01d39 100644 > > > --- a/drivers/irqchip/irq-riscv-intc.c > > > +++ b/drivers/irqchip/irq-riscv-intc.c > > > @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { > > > .xlate = irq_domain_xlate_onecell, > > > }; > > > > > > +static struct fwnode_handle *riscv_intc_hwnode(void) > > > +{ > > > + return (intc_domain) ? intc_domain->fwnode : NULL; > > > +} > > > > This makes no sense. Either you have found the interrupt controller > > and allocated the domain, or you haven't. But you don't register a > > callback without having found it. > > We are registering this callback after creating the INTC domain. Then why are you checking for intc_domain being NULL? > > And you have totally ignored my previous comments about the multitude > > of irq domains for the INTC. Either you get rid of all but one and you > > can register a single fwnode, or you stay with what you have today, > > Only the INTC DT nodes are per-CPU but we are creating only one > INTC domain to manage per-CPU IRQs across all CPUs. Ah, there is this guard that is only valid on the boot CPU. Fair enough. M. -- Without deviation from the norm, progress is not possible.