From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9AB73DA7F4; Mon, 15 Jun 2026 10:04:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781517887; cv=none; b=q6SevbUXxzDyCaFdB+0m65822etJllCjL432wIqr4P8GOXK9nKAoqFeMZVomHzSvZW6mb55aOP3a3g5Zg8XwrUlWwxDAk6Z8rrF/t5WHCtybgGlY/o3p5DeKO7MRluYZWALfrwWGrDC5PiC6IoTkA0V4wl1rw8FpHZgF25cImj0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781517887; c=relaxed/simple; bh=FnPX1yJMcNPD2YXHJwMSrYeEcrrOPYR6rw33JFWjIyA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=DNO4ob4jBtk+CtSQc/+ZOyrqWD27PrftHBAyRjYKLcKiBpsuwoIi9w6/TbFKTveMiJBdloLOxvFFOwmEUgtYXUDKZWoeUaIgOWUl9OIA2na52/a6QSRk1Fwkxal2CkdpiqgyEeK6BVYqziW5JAM0aM3eJo6a62Mugy5Yl7qXYV4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oe8a7Q+z; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oe8a7Q+z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A6FFA1F000E9; Mon, 15 Jun 2026 10:04:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781517886; bh=T9238tsNgBosj+UjEij8wisly1d5TMt1RJ3SiVwn2hc=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=oe8a7Q+zTb0UbAaeKDcms+J7mZxiNdTtTwQ0fseW6a04gdAqA3xTnfJU0xMn6Oxp0 gdiN5x7wDZovEQtfsG7r4zsrtIAwpkqUcKmr7466C/a9p+LQBJaLioW1uk7AQMxiky o1cPvokPDXL6qzp7zKUDeLaPsPl+qvUTg2zuF2hqGU8JEBTGouuywWWQDc+MEXaobK mWegNQQ/uTZuJm+PZyUJgC3WqBUjDT3gMeMyg9hLwCCS20YBJodcM8am38K8XbXy2r wHyAkB/c9EpFQ5qu698NnoJ9UwZHiShSb1MlbROFSI6sXP9yS5Z9ezCJZjQ2cYgozX Js2dz57NJvMvA== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wZ4BQ-0000000CtAJ-0KvG; Mon, 15 Jun 2026 10:04:44 +0000 Date: Mon, 15 Jun 2026 11:08:03 +0100 Message-ID: <87cxxs86bg.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: fuqiang wang , Zenghui Yu , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, dongxu zhang , wangfuqiang49 Subject: Re: [PATCH v2 2/2] KVM: arm64: Skip unreset vCPUs in MPIDR lookup table In-Reply-To: References: <20260611144042.97981-1-fuqiang.wng@gmail.com> <20260611144042.97981-3-fuqiang.wng@gmail.com> <87o6hd8oc7.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@kernel.org, fuqiang.wng@gmail.com, yuzenghui@huawei.com, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, xu910121@sina.com, wangfuqiang49@jd.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 15 Jun 2026 05:20:35 +0100, Oliver Upton wrote: > > On Sun, Jun 14, 2026 at 10:26:32AM +0100, Marc Zyngier wrote: > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > > index 3732ee9eb0d4..fccfa97370df 100644 > > > --- a/arch/arm64/kvm/arm.c > > > +++ b/arch/arm64/kvm/arm.c > > > @@ -887,8 +887,18 @@ static void kvm_init_mpidr_data(struct kvm *kvm) > > > data->mpidr_mask = mask; > > > > > > kvm_for_each_vcpu(c, vcpu, kvm) { > > > - u64 aff = kvm_vcpu_get_mpidr_aff(vcpu); > > > - u16 index = kvm_mpidr_index(data, aff); > > > + u64 aff; > > > + u16 index; > > > + > > > + /* > > > + * Skip vCPUs that haven't been reset yet; their MPIDR_EL1 is > > > + * zero. > > > + */ > > > + if (!kvm_vcpu_mpidr_is_reset(vcpu)) > > > + continue; > > > > But what about the initial loop that computes the significant bits > > amongst the vcpus? > > > > > + > > > + aff = kvm_vcpu_get_mpidr_aff(vcpu); > > > + index = kvm_mpidr_index(data, aff); > > > > In all honesty, I think this is a userspace bug more than anything > > else, and checking for random bits in MPDR_EL1 to verify whether the > > value is plausible is gross. > > +1. Checking the MPIDR value is also broken because userspace can write > whatever it wants to the register, which could even clear the RES1 bit > that's getting tested here. > > > Yhis isn't different from setting MPIDR_EL1 to the same value on all > > vcpus, which we don't try to mitigate. Late setting of MPIDR_EL1 also > > defeats the whole point of having a cache for the affinity to index > > conversion, making SGIs pretty slow for late CPUs. > > > > I really think that by not finalising your vcpus and start running the > > guest, you have cornered yourself pretty badly, and we shouldn't try > > to paper over it. > > I generally agree, although I wouldn't be against a change that nuked > any of the cached routings in case of userspace doing stupid things like > collisions and whatnot. Detecting collisions is difficult, as we have no idea of the overall guest topology. All we can do is work out whether the computed mask has enough bits to represent the number of online vcpus, but that's not necessarily good enough. One possibility would be to invalidate the cache on each update to any MPIDR_EL1, including reset. People doing silly things by initialising vcpus post first start will still suffer, but should we care? Thanks, M. -- Jazz isn't dead. It just smells funny.