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To:     "Zhang, Rui" <rui.zhang@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc:     "Zhuo, Qiuxu" <qiuxu.zhuo@intel.com>,
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        "wei.liu@kernel.org" <wei.liu@kernel.org>,
        "puwen@hygon.cn" <puwen@hygon.cn>,
        "Mehta, Sohil" <sohil.mehta@intel.com>
Subject: Re: [patch V4 28/41] x86/cpu: Provide a sane leaf 0xb/0x1f parser
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 <9cc313b7fdad7c26d561fe390c7e797b81e0323c.camel@intel.com>
Date:   Thu, 17 Aug 2023 11:11:05 +0200
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On Wed, Aug 16 2023 at 12:09, Rui Zhang wrote:
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} else if (tscan->c->topo.ini=
tial_apicid !=3D sl.x2apic_id) {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0pr_warn_once(FW_BUG "CPUID leaf 0x%x subleaf %d APIC
>> ID mismatch %x !=3D %x\n",
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 leaf, subleaf, tscan->c-
>> >topo.initial_apicid, sl.x2apic_id);
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0}
>> +
>
> Maybe worth a warning somewhere if sl.x2apic_shift !=3D
> x86_topo_system.dom_shifts[dom], because invariant x2apic_shift (for
> the same level) among different CPUs is critical for this patch series.
> And I do see variant x2apic_shift on an Intel AlderLake NUC, which has
> been identified to be a microcode bug later.

Yes, we can do that.