From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 668DEC7EE22 for ; Tue, 9 May 2023 08:04:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229562AbjEIIET (ORCPT ); Tue, 9 May 2023 04:04:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235023AbjEIIDv (ORCPT ); Tue, 9 May 2023 04:03:51 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BAAAA265 for ; Tue, 9 May 2023 01:02:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683619362; x=1715155362; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=HyMZvjVK4PWg2zKaACEjXyLpCS8bkLdXvTElw8PwpKo=; b=AUGu+MgzBemJbCkH08CBCLnNqT0CcNVL05iKitJDpslNMaQPiR5PUzrU fHBLR+SuIAP3SjRFOswbWwrbdbiWwwUmxQfC5/YlNn50SuqnyIC9wS3k0 g+JL5PCwYtToLbRGFMzuc65kdQBlT39G+GinT0l4vp50kOD1PNfDJoC5V xBrq5fJgDYMsBoQ8Q6+CC56KF37gTbqfjn27FmLYdz6i6MH2byqu6Gbty iix7LQimtJbBYI75KLFjZf+n2ewLaHnwa1YEi98rpnU/YTeX+uDzbkPpw vxgMStbB2vaBJDVuOfcdhjZmTFHyWOVF59mUEB1Sx/DaWQ/t/JkCl4OmG w==; X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="413102010" X-IronPort-AV: E=Sophos;i="5.99,261,1677571200"; d="scan'208";a="413102010" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2023 00:57:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="945165860" X-IronPort-AV: E=Sophos;i="5.99,261,1677571200"; d="scan'208";a="945165860" Received: from unknown (HELO localhost) ([10.252.39.92]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2023 00:57:21 -0700 From: Jani Nikula To: Lucas De Marchi , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Andy Shevchenko , Thomas Gleixner , linux-kernel@vger.kernel.org, Masahiro Yamada , Andrew Morton , Kevin Brodsky , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Lucas De Marchi Subject: Re: [PATCH 3/3] drm/i915: Temporary conversion to new GENMASK/BIT macros In-Reply-To: <20230509051403.2748545-4-lucas.demarchi@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20230509051403.2748545-1-lucas.demarchi@intel.com> <20230509051403.2748545-4-lucas.demarchi@intel.com> Date: Tue, 09 May 2023 10:57:19 +0300 Message-ID: <87cz3andi8.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 08 May 2023, Lucas De Marchi wrote: > Convert the REG_* macros from i915_reg_defs.h to use the new macros > defined in linux/bits.h. This is just to help on the implementation > of the new macros and not intended to be applied. This drops a number of build time input checks as well as casts to the specified types. BR, Jani. > > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/i915_reg_defs.h | 28 +++++----------------------- > 1 file changed, 5 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h > index 622d603080f9..61fbb8d62b25 100644 > --- a/drivers/gpu/drm/i915/i915_reg_defs.h > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h > @@ -17,10 +17,7 @@ > * > * @return: Value with bit @__n set. > */ > -#define REG_BIT(__n) \ > - ((u32)(BIT(__n) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ > - ((__n) < 0 || (__n) > 31)))) > +#define REG_BIT(__n) BIT_U32(__n) > > /** > * REG_BIT8() - Prepare a u8 bit value > @@ -30,10 +27,7 @@ > * > * @return: Value with bit @__n set. > */ > -#define REG_BIT8(__n) \ > - ((u8)(BIT(__n) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ > - ((__n) < 0 || (__n) > 7)))) > +#define REG_BIT8(__n) BIT_U8(__n) > > /** > * REG_GENMASK() - Prepare a continuous u32 bitmask > @@ -44,11 +38,7 @@ > * > * @return: Continuous bitmask from @__high to @__low, inclusive. > */ > -#define REG_GENMASK(__high, __low) \ > - ((u32)(GENMASK(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) > +#define REG_GENMASK(__high, __low) GENMASK_U32(__high, __low) > > /** > * REG_GENMASK64() - Prepare a continuous u64 bitmask > @@ -59,11 +49,7 @@ > * > * @return: Continuous bitmask from @__high to @__low, inclusive. > */ > -#define REG_GENMASK64(__high, __low) \ > - ((u64)(GENMASK_ULL(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 63 || (__low) > (__high))))) > +#define REG_GENMASK64(__high, __low) GENMASK_ULL(__high, __low) > > /** > * REG_GENMASK8() - Prepare a continuous u8 bitmask > @@ -74,11 +60,7 @@ > * > * @return: Continuous bitmask from @__high to @__low, inclusive. > */ > -#define REG_GENMASK8(__high, __low) \ > - ((u8)(GENMASK(__high, __low) + \ > - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ > - __is_constexpr(__low) && \ > - ((__low) < 0 || (__high) > 7 || (__low) > (__high))))) > +#define REG_GENMASK8(__high, __low) GENMASK_U8(__high, __low) > > /* > * Local integer constant expression version of is_power_of_2(). -- Jani Nikula, Intel Open Source Graphics Center