From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FDE5C433FE for ; Wed, 13 Oct 2021 14:52:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A3D66109E for ; Wed, 13 Oct 2021 14:52:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237194AbhJMOyS (ORCPT ); Wed, 13 Oct 2021 10:54:18 -0400 Received: from relay2-d.mail.gandi.net ([217.70.183.194]:60393 "EHLO relay2-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234388AbhJMOyQ (ORCPT ); Wed, 13 Oct 2021 10:54:16 -0400 Received: (Authenticated sender: gregory.clement@bootlin.com) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id E7BEA40010; Wed, 13 Oct 2021 14:52:07 +0000 (UTC) From: Gregory CLEMENT To: Chris Packham , andrew@lunn.ch, sebastian.hesselbarth@gmail.com, robh+dt@kernel.org, kostap@marvell.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: Re: [PATCH 1/2] arm/arm64: dts: Enable 2.5G Ethernet port on CN9130-CRB In-Reply-To: <20211007230619.957016-2-chris.packham@alliedtelesis.co.nz> References: <20211007230619.957016-1-chris.packham@alliedtelesis.co.nz> <20211007230619.957016-2-chris.packham@alliedtelesis.co.nz> Date: Wed, 13 Oct 2021 16:52:02 +0200 Message-ID: <87czo9dlkd.fsf@BL-laptop> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Chris, > Enable the 2.5G Ethernet port by setting the status to "okay" and the > phy-mode to "2500base-x" on the cn9130-crb boards. Tested on a > CN9130-CRB-A. > > Signed-off-by: Chris Packham As I am not sure that next week the pull request will be accepted when you will send the v2 for the second patch, I already applied the one on mvebu/dt64 Thanks, Gregory > --- > > The Marvell SDK adds 2500base-t and uses it in the equivalent dtsi but > looking at the documentation for both the SoC and the PHY I think > 2500base-x is correct for the system interface (the line side is > 2500base-t). > > arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi > index 505ae69289f6..e7918f325646 100644 > --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi > +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi > @@ -214,8 +214,8 @@ &cp0_eth1 { > }; > > &cp0_eth2 { > - /* This port uses "2500base-t" phy-mode */ > - status = "disabled"; > + status = "okay"; > + phy-mode = "2500base-x"; > phy = <&nbaset_phy0>; > phys = <&cp0_comphy5 2>; > }; > -- > 2.33.0 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com