From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6C01C4338F for ; Tue, 27 Jul 2021 13:00:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF952610E9 for ; Tue, 27 Jul 2021 13:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236543AbhG0NAF (ORCPT ); Tue, 27 Jul 2021 09:00:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:48392 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232067AbhG0NAD (ORCPT ); Tue, 27 Jul 2021 09:00:03 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 18DA861A87; Tue, 27 Jul 2021 13:00:04 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m8Mgk-001IlW-01; Tue, 27 Jul 2021 14:00:02 +0100 Date: Tue, 27 Jul 2021 14:00:01 +0100 Message-ID: <87czr3ewtq.wl-maz@kernel.org> From: Marc Zyngier To: Bixuan Cui Cc: , , , , , , , , , , , , , Subject: Re: [PATCH -next v2] iommu/arm-smmu-v3: Add suspend and resume support In-Reply-To: <20210727121408.81883-1-cuibixuan@huawei.com> References: <20210727121408.81883-1-cuibixuan@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: cuibixuan@huawei.com, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, will@kernel.org, weiyongjun1@huawei.com, john.wanghui@huawei.com, dingtianhong@huawei.com, thunder.leizhen@huawei.com, guohanjun@huawei.com, robin.murphy@arm.com, joro@8bytes.org, jean-philippe@linaro.org, Jonathan.Cameron@huawei.com, song.bao.hua@hisilicon.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 27 Jul 2021 13:14:08 +0100, Bixuan Cui wrote: > > Add suspend and resume support for arm-smmu-v3 by low-power mode. > > When the smmu is suspended, it is powered off and the registers are > cleared. So saves the msi_msg context during msi interrupt initialization > of smmu. When resume happens it calls arm_smmu_device_reset() to restore > the registers. > > Signed-off-by: Bixuan Cui > Reviewed-by: Wei Yongjun > Reviewed-by: Zhen Lei > Reviewed-by: Ding Tianhong > Reviewed-by: Hanjun Guo > --- > Changes in v2: > * Using get_cached_msi_msg() instead of the descriptor to resume msi_msg > in arm_smmu_resume_msis(); > > * Move arm_smmu_resume_msis() from arm_smmu_setup_unique_irqs() into > arm_smmu_setup_irqs() and rename it to arm_smmu_resume_unique_irqs(); > > Call arm_smmu_setup_unique_irqs() to configure the IRQ during probe and > call arm_smmu_resume_unique_irqs() in resume mode to restore the IRQ > registers to make the code more reasonable. > > * Call arm_smmu_device_disable() to disable smmu and clear CR0_SMMUEN on > suspend. Then the warning about CR0_SMMUEN being enabled can be cleared > on resume. > > * Using SET_SYSTEM_SLEEP_PM_OPS(); > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 69 ++++++++++++++++++--- > 1 file changed, 62 insertions(+), 7 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 235f9bdaeaf2..66f35d5c7a70 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -40,6 +40,7 @@ MODULE_PARM_DESC(disable_bypass, > > static bool disable_msipolling; > module_param(disable_msipolling, bool, 0444); > +static bool bypass; As outlined before, this is likely to be wrong if you can have per-SMMU bypass control. > MODULE_PARM_DESC(disable_msipolling, > "Disable MSI-based polling for CMD_SYNC completion."); > > @@ -3129,11 +3130,38 @@ static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) > doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; > doorbell &= MSI_CFG0_ADDR_MASK; > > + /* Saves the msg context for resume if desc->msg is empty */ > + if (desc->msg.address_lo == 0x0 && desc->msg.address_hi == 0x0) { > + desc->msg.address_lo = msg->address_lo; > + desc->msg.address_hi = msg->address_hi; > + desc->msg.data = msg->data; > + } I thought I had made it clear that this approach is not acceptable. Please fix the generic code to keep track of the latest message. Thanks, M. -- Without deviation from the norm, progress is not possible.