From: Andi Kleen <andi@firstfloor.org>
To: Hans Schou <linux@schou.dk>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] SiS55x, another x86 CPU
Date: Mon, 13 Oct 2008 07:58:41 +0200 [thread overview]
Message-ID: <87d4i5rq7i.fsf@basil.nowhere.org> (raw)
In-Reply-To: <Pine.LNX.4.64.0810111143210.23344@sko.w0.dk> (Hans Schou's message of "Sat, 11 Oct 2008 23:24:42 +0200 (CEST)")
Hans Schou <linux@schou.dk> writes:
> flags : fpu tsc cx8 mmx
>
> Instruction and data cache is 8KB each it says in the datasheet. I'm
> not sure but it does not look like it is written in dmesg.
>
> ACPI sleep supports S1 S2 S3 S4 S5.
>
> CPU power states supports C0 C1 C2 C3.
>
> See attachment. (I hope it gets here!)
Your attachment seems to be windows line end damaged.
Also the changes are so small that it's not worth adding a CONFIG
for it. Just add it unconditionally.
And hardcoding the cache size for all of SiS seems a bit extreme.
What happens when SiS ever brings out another part with different caches?
Ideally figure out some way to detect this particular CPU and only
use 8 KB only for that. Alternatively ignore it (there's nothing
really in the kernel that uses the cache sizes anyways)
-Andi
next prev parent reply other threads:[~2008-10-13 5:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-11 21:24 [PATCH] SiS55x, another x86 CPU Hans Schou
2008-10-13 5:58 ` Andi Kleen [this message]
2008-10-13 20:56 ` Hans Schou
2008-10-14 6:06 ` Andi Kleen
2008-10-14 17:38 ` Hans Schou
2008-10-15 10:06 ` Andi Kleen
2008-10-15 19:51 ` Geert Uytterhoeven
2008-10-15 22:37 ` Hans Schou
2008-10-16 7:09 ` Geert Uytterhoeven
2008-10-16 19:01 ` Hans Schou
2008-10-16 19:18 ` Maciej W. Rozycki
2008-10-16 20:13 ` Hans Schou
2008-10-15 22:24 ` Hans Schou
[not found] ` <48F6E3DE.10206@zytor.com>
2008-10-16 18:47 ` Hans Schou
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