From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F40562FC01B; Sun, 5 Jul 2026 19:25:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783279550; cv=none; b=M8acPCKsLoGVrJiST1rY/hXMUGjjbrD8mMsYO7EklGU/CgZXWZ1dFELvC8+6eDVFJTj4lM9jS+Hs7hj+erbF4JNCrhSInIEBK3iXn0IgnSLxR03t6u/I/v1/ZE7IXvdYPpwcfXM1YyuSE6/GxRQjVKju9QfzdeyAAqXM+YUYy2Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783279550; c=relaxed/simple; bh=KeFIokG0C7O2yN256TOKgtfjvTcpRnMR8yDALgFm+7Q=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=PP5Mi0yfBzbEOY8ibZRvolS/SKbU/2avLgl7H+7uC6oxdnTKQLqJvNMziqnyxmYSNy6StLpH0U+dUOdCcAXUhGZELCh2Dg235bH6pIgDzXde0tEUWENs/UydTyy9sKGNITAFtqAgyM3R+Y6Aa1tGtZ6n02Ky+lz3Zecx/WbbKqY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QKAn6fqm; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QKAn6fqm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88CD51F000E9; Sun, 5 Jul 2026 19:25:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783279548; bh=OPI+ApKqdzBUwz1sXIFVIUKT6N0yjrQCNo8ScPon0rE=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=QKAn6fqmHWbVb6fQ26XB5SXr8dfPE/yyl6eeEnIY4buUZrRYYnOLCXflQL468TJXv g2bWXPkBhcuLddlkoEPAdslZykWk5gnMk1i7KQtunwTrY+f6LUH7AqI2tUlvRkLnSZ 7JnRUD+nuA01QSzTm+gvIoizkdplV7cQBK00trh3Evme0/iaawGzFmWFjoqHSPG8G3 Yi+nvqlGxjXJ9RZC4kO3SjRvVxIsKL1w5XPlr7GxqBHJah9PWmDDmZ6RgACsKdLXf9 /gm7Ffyk72sC4AG1pQ6wpkcQ2ITzqetGFl46xPxtLoDUn4YH/tuuvVT6FI5d41fk9j vgl+yMGcSPNRA== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wgSTK-00000001frG-14pI; Sun, 05 Jul 2026 19:25:46 +0000 Date: Sun, 05 Jul 2026 20:27:34 +0100 Message-ID: <87echh6xuh.wl-maz@kernel.org> From: Marc Zyngier To: Dev Jain Cc: Bradley Morgan , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Quentin Perret , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4] KVM: arm64: Record whether pKVM stage 2 mapping is cacheable In-Reply-To: References: <20260701192428.17430-1-include@grrlz.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: dev.jain@arm.com, include@grrlz.net, oupton@kernel.org, tabba@google.com, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, qperret@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sun, 05 Jul 2026 15:08:58 +0100, Dev Jain wrote: > > > > On 02/07/26 12:54 am, Bradley Morgan wrote: > > pKVM keeps its own mapping list for stage 2 operations. Its flush path > > uses that list directly, so it lost the PTE attribute check done by the > > generic stage 2 walker. > > > > Record whether a mapping is cacheable and skip cache maintenance for > > mappings that are not cacheable. > > > > Fixes: e912efed485a ("KVM: arm64: Introduce the EL1 pKVM MMU") > > Is Fixes tag required? If I am reading correctly, Arm ARM says this: > > "For VA-based cache maintenance instructions, the instruction operates on the > caches regardless of the memory type and cacheability attributes marked for > the memory address in the VMSA translation table entries. This means that > the effects of the cache maintenance instructions can apply regardless of: > Whether the address accessed: > Is Normal memory or Device memory. > Has the Cacheable attribute or the Non-cacheable attribute." > > So nothing goes wrong if we do dcache clean for non-cacheable > memory. Two things: - having to perform CMOs for something that is not *expected* to be cacheable is both pointless and a contradiction of the intent - what you quote is about the nature of the *mapping*, and not the memory that is being mapped. Cleaning a dirty cache line on an unsuspecting MMIO endpoint is never going to end nicely. Just have a try. My reading of all this is that a fix indeed is required, and therefore a Fixes tag *must* be present. M. -- Jazz isn't dead. It just smells funny.