Re: [PATCH v3 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode

[Thomas Gleixner <tglx@kernel.org>]

On Tue, Jun 16 2026 at 14:55, Maulik Shah wrote:
> All PDC irqchip supports pass through mode in which both Direct SPIs and

All PDC variants support pass .. ??

> GPIO IRQs (as SPIs) are sent to GIC without latching at PDC.
>
> Newer PDCs (v3.0 onwards) also support additional secondary controller mode
> where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs

latches the GPIO interrupts and sends them to GIC as level type interrupts.

> still works same as pass through mode without latching at PDC even in

SPIs .. work the same as pass-through mode ....

> secondary controller mode.
>
> All the SoCs so far default uses pass through mode with the exception of

SoCs ... use pass-through 

> x1e. x1e PDC may be set to secondary controller mode for builds on CRD
> boards whereas it may be set to pass through mode for IoT-EVK boards.
> The mode configuration is done in firmware and initially shipped windows
> firmware did not have SCM interface to read or modify the PDC mode.
> Later only write access is opened up for non secure world.

.. for the non-secure ..

> +/**
> + * qcom_pdc_gic_set_type: Configure PDC for the interrupt
> + *
> + * @d: the interrupt data
> + * @type: the interrupt type

https://docs.kernel.org/process/maintainer-tip.html#struct-declarations-and-initializers

I'm sure I pointed you to that document before.

> + *
> + * All @type are forwarded as Level type to parent GIC
> + */
> +static int qcom_pdc_gic_secondary_set_type(struct irq_data *d, unsigned int type)
> +{
> +	enum pdc_irq_config_bits pdc_type;
> +	enum pdc_irq_config_bits old_pdc_type;

Chapter before the above ...

> @@ -449,8 +628,13 @@ static int pdc_setup_pin_mapping(struct device *dev, struct device_node *np)
>  		if (ret)
>  			return ret;
>  
> -		for (int i = 0; i < pdc->region[n].cnt; i++)
> -			pdc->enable_intr(i + pdc->region[n].pin_base, 0);
> +		for (int i = 0; i < pdc->region[n].cnt; i++) {
> +			if (pdc_pin_is_gpio(i + pdc->region[n].pin_base) &&
> +			    pdc->mode == PDC_SECONDARY_MODE)
> +				pdc->clear_gpio(i + pdc->region[n].pin_base);
> +

Requires guard(irqsave)(...)