From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1297A1A275 for ; Mon, 11 May 2026 15:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778514334; cv=none; b=ltY8lG3zKBtaU72txPjd8nLAoueB2bq9V3B68i+EQzfQxRtJLJqsUHzToXxMQ/j4ECln9iViWK19+JLEcvEO6RAFOiIm3LsCW4PnLFbd02hFKLdQrYs6CqE7uJx6gA4bOv9+eQnfzRRD6pf75CbTNEecerVE8hX751VM/bKDQBY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778514334; c=relaxed/simple; bh=Y18W+CCSpt3+mv2Vx8zjNUKxv9sohnSJ9WiNGiFH04I=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=JqXSEzNtNgCVX95qwsmxNTlIRfdLqkWpHwuid7MWhAzpei1m1fIPu/LlJuezOqIyDBmvMKGwYRzCHgEIROQJI3LtDA9NS002dpkCGgNTka6RQAIQ0eztiAHcUNOsrhAIeAoEL1w6U3NMzRv0Du+YJ68cADqe6ojziGJG6jq6Vow= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KAEtjRsc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KAEtjRsc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CDE21C2BCB0; Mon, 11 May 2026 15:45:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778514333; bh=Y18W+CCSpt3+mv2Vx8zjNUKxv9sohnSJ9WiNGiFH04I=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=KAEtjRsckCvjhlS/SriD8u/4TvzO9zwZTjzbbhscYnYYKj2skvIEizYuQg4o9poXh biT3KkEZILSg8S03Lu2cbfA7F7mK2upf45oz8/HY9COS3calDEmXJYqNlaqO3+gLY9 eQmDwQlN97WyONcUhZRmjpVKVF632RmIk6E4S1viJLABIJQJHf65GVpgTFB5OhG5zh wwNnCtva5gjGYS042bWIaeGaWtpo7igZFnUJ0/LIa66ehyRNM0ci0vwmLYZ6pUjuly POpXHREYNQKaNgIB9of3buhaOr0LfkFTYIkey+eceCdHLOe0X6w8cH2LMxMA+Y8Xhn dO4mOv9CFbkuQ== From: Thomas Gleixner To: Michael Kelley , LKML Cc: "x86@kernel.org" , Dmitry Ilvokhin , Radu Rendec , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Subject: RE: [patch V5 00/15] Improve /proc/interrupts further In-Reply-To: References: <20260401195625.213446764@kernel.org> Date: Mon, 11 May 2026 17:45:30 +0200 Message-ID: <87ecji7xwl.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu, Apr 02 2026 at 02:32, Michael Kelley wrote: > On x86, the leftmost column now correctly aligns the "VPMI:" label. > But the rightmost column does not correctly align the text > "Perf Guest Mediated PMI". It needs one additional space. Here's my > output (with some CPU columns removed so it's not so wide): > > root@mhkubun:~# cat /proc/interrupts | cut -b 1-30,64- > CPU0 CPU1 CPU5 CPU6 CPU7 > PIW: 0 0 0 0 0 Posted-interrupt wakeup event > VPMI: 0 0 0 0 0 Perf Guest Mediated PMI Right. There is a missing space in the VPMI text. > On arm64, the leftmost column doesn't align the IPI entries. > Neither does the rightmost column for the IPI entries. Here's some > of my output: > > 45: 0 0 80 0 0 HV-PCI-MSIX-0817:00:02.0 14 Edge mlx5_comp13@pci:0817:00:02.0 > 46: 0 0 0 10 0 HV-PCI-MSIX-0817:00:02.0 15 Edge mlx5_comp14@pci:0817:00:02.0 > 47: 0 0 0 0 45 HV-PCI-MSIX-0817:00:02.0 16 Edge mlx5_comp15@pci:0817:00:02.0 > IPI0: 906 536 649 495 606 Rescheduling interrupts > IPI1: 28844 12457 14770 55242 39175 Function call interrupts > IPI2: 0 0 0 0 0 CPU stop interrupts > IPI3: 0 0 0 0 0 CPU stop NMIs > IPI4: 0 0 0 0 0 Timer broadcast interrupts > IPI5: 11 1 5 0 2 IRQ work interrupts > IPI6: 0 0 0 0 0 CPU backtrace interrupts > IPI7: 0 0 0 0 0 KGDB roundup interrupts That means total_nr_irqs is < 1000, which makes it use precision of 3. That obiously is not enough for the IPIn output and already an issue today. The IPI text is misaligned on ARM64 already today in pretty much the same way as with the patches applied. That's trivial to fix. As a bonus ARM(64) has quite some interrupt chips which have their own print routine to show the interupt chip name. That makes it even more randomly aligned. That's also an existing problem and a larger effort to mop up and as it's already a mess. I leave it so. x86 suffers from the leftmost column issue as well when you make NR_CPUS small enough in case that VPMI is emitted because the default precision in the core is 3 digits. Thanks, tglx