From: Thomas Gleixner <tglx@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>
Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 4/6] irqchip/renesas-rzv2h: Make IRQ type handling range-aware
Date: Tue, 24 Feb 2026 08:30:39 +0100 [thread overview]
Message-ID: <87ecmavbs0.ffs@tglx> (raw)
In-Reply-To: <20260209104121.26172-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Mon, Feb 09 2026 at 10:41, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Refine IRQ type handling to explicitly bound IRQ and TINT ranges and
> dispatch based on the hardware IRQ number.
Changelog should not start with an explanation of the what. See
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog
> This restructures the logic to clearly separate NMI, IRQ, and TINT
Restructure the ...
> @@ -175,18 +177,27 @@ static void rzv2h_icu_eoi(struct irq_data *d)
> u32 bit;
>
> scoped_guard(raw_spinlock, &priv->lock) {
> - if (hw_irq >= ICU_TINT_START) {
> - tintirq_nr = hw_irq - ICU_TINT_START;
> - bit = BIT(tintirq_nr);
> - if (!irqd_is_level_type(d))
> - writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
> - } else if (hw_irq >= ICU_IRQ_START) {
> + switch (hw_irq) {
> + case 0:
> + /* Clear NMI */
> + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);
> + break;
> + case ICU_IRQ_START ... ICU_IRQ_LAST:
> + /* Clear IRQ */
> tintirq_nr = hw_irq - ICU_IRQ_START;
> bit = BIT(tintirq_nr);
> if (!irqd_is_level_type(d))
> writel_relaxed(bit, priv->base + ICU_ISCLR);
> - } else {
> - writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);
> + break;
> + case ICU_TINT_START ... ICU_TINT_LAST:
> + /* Clear TINT */
> + tintirq_nr = hw_irq - ICU_TINT_START;
> + bit = BIT(tintirq_nr);
> + if (!irqd_is_level_type(d))
> + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
> + break;
> + default:
> + break;
> }
> }
TBH, I personally do not care about the performance of your platform at
all, but are you really serious about having a switch case like that in
a hotpath function?
Instead of sprinkling this switch case gunk all over the place you can
simply have separate interrupt chips for each region and install the
proper one at setup time. Then the functions are clearly separated and
just handling the type they are written for and nothing else. No?
Thanks,
tglx
next prev parent reply other threads:[~2026-02-24 7:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-09 10:41 [PATCH v3 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger Prabhakar
2026-02-09 10:41 ` [PATCH v3 1/6] irqchip/renesas-rzv2h: Use local node pointer Prabhakar
2026-02-09 10:41 ` [PATCH v3 2/6] irqchip/renesas-rzv2h: Use local device pointer in ICU probe Prabhakar
2026-02-09 10:41 ` [PATCH v3 3/6] irqchip/renesas-rzv2h: Switch to using dev_err_probe() Prabhakar
2026-02-09 10:41 ` [PATCH v3 4/6] irqchip/renesas-rzv2h: Make IRQ type handling range-aware Prabhakar
2026-02-24 7:30 ` Thomas Gleixner [this message]
2026-02-24 13:41 ` Lad, Prabhakar
2026-02-09 10:41 ` [PATCH v3 5/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support Prabhakar
2026-02-24 7:34 ` Thomas Gleixner
2026-02-24 15:36 ` Lad, Prabhakar
2026-02-09 10:41 ` [PATCH v3 6/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger Prabhakar
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